FreeBSD The Power to Serve

NXP DPAA2 support

Contact: Dmitry Salychev <dsl@FreeBSD.org>
Contact: Bjoern A. Zeeb <bz@FreeBSD.org>

What is DPAA2?

DPAA2 is a hardware-level networking architecture found in some NXP SoCs which contains hardware blocks including Management Complex (MC, a command interface to manipulate DPAA2 objects), Wire Rate I/O processor (WRIOP, packets distribution, queuing, drop decisions), Queues and Buffers Manager (QBMan, Rx/Tx queues control, Rx buffer pools) and others. The Management Complex runs NXP-supplied firmware which provides DPAA2 objects as an abstraction layer over those blocks to simplify access to the underlying hardware.

Changes from the previous report

Work in Progress

Work on dev/sff started to support SFF/SFP modules in order to test DPAA2 drivers on links above 1 Gbit/s.

Plan

  • Heavy network load tests (2.5 Gbit/s, 10 Gbit/s) and bottlenecks mitigation.

  • Cached memory-backed software portals.

  • Driver resources de-allocation to unload dpaa2.ko properly.

  • Further parts (DPSW, DCE, etc.) supported by the hardware.

Sponsor: Traverse Technologies (providing Ten64 HW for testing)


Last modified on: October 2, 2023 by Dmitry Salychev