Links:
Wiki Homepage URL: https://wiki.freebsd.org/riscv

Contact: Mitchell Horne <mhorne@FreeBSD.org>

The FreeBSD/RISC-V project is providing support for running FreeBSD on the RISC-V Instruction Set Architecture.

This quarter I resumed work on improvements to FreeBSD’s RISC-V architecture support (riscv64). Work was focused primarily on small bug-fixes and improvements, and tooling. A handful of known panics and bug reports were fixed and closed.

On the performance tooling side, some issues with the use of DTrace on riscv64 were found and addressed. Specifically, backtraces produced by the stack() function were not being captured correctly. First, a change was made to the compiler flags to ensure that kernel modules always make use of the frame pointer, so that unwinding the kernel stack works as expected. Second, some tweaks were made to machine-dependent DTrace code in the profile and fbt providers, making the correct number of frames appear in each backtrace. Now, DTrace can be used to accurately capture profiling data on this platform, enabling the generation of flamegraphs.

I also began porting the hwpmc(4) driver to run on this platform. Unlike other ISAs, RISC-V does not standardize the set of counter events that a CPU must support, nor are the programmable event selection registers accessible to the kernel. To work around this, there is an SBI "Performance Monitoring Unit" extension which provides an abstracted interface for managing such functionality. The new hwpmc(4) class is written to use this interface. Current generation RISC-V hardware supports incrementing performance counters, but lacks the counter overflow interrupts required to enable sampling PMCs.

Work is expected to continue next quarter. Aside from the in-progress items mentioned, focus will be given to the following areas:

Sponsor: The FreeBSD Foundation