Medium-sized superpages on arm64 and beyond
The 64-bit ARM architecture’s page table descriptor format contains a flag called the Contiguous bit. This tells the MMU that it can cache an aligned, physically contiguous group of 16 page table entries which have identical permissions and attributes using only 1 TLB entry.
The Contiguous bit, as well as the conceptually similar Svnapot extension to the RISC-V architecture, allows for the use of 64 KiB superpages. These medium-sized superpages can bring to smaller memory objects the address-translation speedup typically associated with more traditional 2 MiB superpages.
This project focuses on bringing support for medium-sized superpages to FreeBSD. So far, we have modified the arm64 pmap code to automatically utilize 64 KiB superpages by detecting physically contiguous page table entries and promoting them using the Contiguous bit. Now, we are working to adapt the kernel’s superpage reservation module to support 64 KiB reservations in addition to the current 2 MiB ones. Adding medium-sized reservations will allow the virtual memory system to explicitly allocate pieces of memory which fit the requirements for superpage promotion, rather than just hoping that they occur by chance.
Our goal is to accomplish this in a general way that makes it possible to specify multiple arbitrary power-of-two reservation sizes, making it easier to take advantage of hardware features on other architectures like Ryzen’s PTE Coalescing, which transparently merges groups of 4 KiB page table entries into medium-sized superpages.
Sponsor: Department of Computer Science, Rice University
Last modified on: August 2, 2022 by Lorenzo Salvadore