--- contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp.orig
+++ contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -1285,6 +1285,8 @@
           continue;
 
         MCRegister Reg = MO.getReg();
+        if (!Reg)
+          continue;
 
         // This picks up sibling registers (e.q. %al -> %ah).
         for (MCRegUnit Unit : TRI.regunits(Reg))
@@ -1308,8 +1310,11 @@
         if (!MO.isReg())
           continue;
 
-        for (const MCPhysReg &Reg :
-             TRI.sub_and_superregs_inclusive(MO.getReg()))
+        MCRegister Reg = MO.getReg();
+        if (!Reg)
+          continue;
+
+        for (const MCPhysReg Reg : TRI.sub_and_superregs_inclusive(Reg))
           RegsToZero.reset(Reg);
       }
     }