Skip site navigation (1)Skip section navigation (2)

FreeBSD Manual Pages

  
 
  

home | help
PMC.COREI7(3)	       FreeBSD Library Functions Manual		 PMC.COREI7(3)

NAME
     pmc.corei7	-- measurement events for Intel	Core i7	and Xeon 5500 family
     CPUs

LIBRARY
     Performance Counters Library (libpmc, -lpmc)

SYNOPSIS
     #include <pmc.h>

DESCRIPTION
     Intel Core	i7 CPUs	contain	PMCs conforming	to version 2 of	the Intel per-
     formance measurement architecture.	 These CPUs may	contain	up to three
     classes of	PMCs:

     PMC_CLASS_IAF     Fixed-function counters that count only one hardware
		       event per counter.

     PMC_CLASS_IAP     Programmable counters that may be configured to count
		       one of a	defined	set of hardware	events.

     The number	of PMCs	available in each class	and their widths need to be
     determined	at run time by calling pmc_cpuinfo(3).

     Intel Core	i7 and Xeon 5500 PMCs are documented in	"Volume	3B: System
     Programming Guide,	Part 2", Intel(R) 64 and IA-32 Architectures Software
     Developes Manual, Order Number: 253669-033US, Intel Corporation, December
     2009.

   COREI7 AND XEON 5500	FIXED FUNCTION PMCS
     These PMCs	and their supported events are documented in pmc.iaf(3).  Not
     all CPUs in this family implement fixed-function counters.

   COREI7 AND XEON 5500	PROGRAMMABLE PMCS
     The programmable PMCs support the following capabilities:

     Capability		  Support
     PMC_CAP_CASCADE	  No
     PMC_CAP_EDGE	  Yes
     PMC_CAP_INTERRUPT	  Yes
     PMC_CAP_INVERT	  Yes
     PMC_CAP_READ	  Yes
     PMC_CAP_PRECISE	  No
     PMC_CAP_SYSTEM	  Yes
     PMC_CAP_TAGGING	  No
     PMC_CAP_THRESHOLD	  Yes
     PMC_CAP_USER	  Yes
     PMC_CAP_WRITE	  Yes

   Event Qualifiers
     Event specifiers for these	PMCs support the following common qualifiers:

     rsp=value
	     Configure the Off-core Response bits.

	     DMND_DATA_RD
		     Counts the	number of demand and DCU prefetch data reads
		     of	full and partial cachelines as well as demand data
		     page table	entry cacheline	reads. Does not	count L2 data
		     read prefetches or	instruction fetches.

	     DMND_RFO
		     Counts the	number of demand and DCU prefetch reads	for
		     ownership (RFO) requests generated	by a write to data
		     cacheline.	Does not count L2 RFO.

	     DMND_IFETCH
		     Counts the	number of demand and DCU prefetch instruction
		     cacheline reads. Does not count L2	code read prefetches.
		     WB	Counts the number of writeback (modified to exclusive)
		     transactions.

	     PF_DATA_RD
		     Counts the	number of data cacheline reads generated by L2
		     prefetchers.

	     PF_RFO  Counts the	number of RFO requests generated by L2
		     prefetchers.

	     PF_IFETCH
		     Counts the	number of code reads generated by L2 prefetch-
		     ers.

	     OTHER   Counts one	of the following transaction types, including
		     L3	invalidate, I/O, full or partial writes, WC or non-
		     temporal stores, CLFLUSH, Fences, lock, unlock, split
		     lock.

	     UNCORE_HIT
		     L3	Hit: local or remote home requests that	hit L3 cache
		     in	the uncore with	no coherency actions required (snoop-
		     ing).

	     OTHER_CORE_HIT_SNP
		     L3	Hit: local or remote home requests that	hit L3 cache
		     in	the uncore and was serviced by another core with a
		     cross core	snoop where no modified	copies were found
		     (clean).

	     OTHER_CORE_HITM
		     L3	Hit: local or remote home requests that	hit L3 cache
		     in	the uncore and was serviced by another core with a
		     cross core	snoop where modified copies were found (HITM).

	     REMOTE_CACHE_FWD
		     L3	Miss: local homed requests that	missed the L3 cache
		     and was serviced by forwarded data	following a cross
		     package snoop where no modified copies found. (Remote
		     home requests are not counted)

	     REMOTE_DRAM
		     L3	Miss: remote home requests that	missed the L3 cache
		     and were serviced by remote DRAM.

	     LOCAL_DRAM
		     L3	Miss: local home requests that missed the L3 cache and
		     were serviced by local DRAM.

	     NON_DRAM
		     Non-DRAM requests that were serviced by IOH.

     cmask=value
	     Configure the PMC to increment only if the	number of configured
	     events measured in	a cycle	is greater than	or equal to value.

     edge    Configure the PMC to count	the number of de-asserted to asserted
	     transitions of the	conditions expressed by	the other qualifiers.
	     If	specified, the counter will increment only once	whenever a
	     condition becomes true, irrespective of the number	of clocks dur-
	     ing which the condition remains true.

     inv     Invert the	sense of comparison when the ``cmask'' qualifier is
	     present, making the counter increment when	the number of events
	     per cycle is less than the	value specified	by the ``cmask'' qual-
	     ifier.

     os	     Configure the PMC to count	events happening at processor privi-
	     lege level	0.

     usr     Configure the PMC to count	events occurring at privilege levels
	     1,	2 or 3.

     If	neither	of the ``os'' or ``usr'' qualifiers are	specified, the default
     is	to enable both.

   Event Specifiers (Programmable PMCs)
     Core i7 and Xeon 5500 programmable	PMCs support the following events:

     SB_DRAIN.ANY
	     (Event 04H, Umask 07H) Counts the number of store buffer drains.

     STORE_BLOCKS.AT_RET
	     (Event 06H, Umask 04H) Counts number of loads delayed with	at-
	     Retirement	block code. The	following loads	need to	be executed at
	     retirement	and wait for all senior	stores on the same thread to
	     be	drained: load splitting	across 4K boundary (page split), load
	     accessing uncacheable (UC or USWC)	memory,	load lock, and load
	     with page table in	UC or USWC memory region.

     STORE_BLOCKS.L1D_BLOCK
	     (Event 06H, Umask 08H) Cacheable loads delayed with L1D block
	     code

     PARTIAL_ADDRESS_ALIAS
	     (Event 07H, Umask 01H) Counts false dependency due	to partial
	     address aliasing

     DTLB_LOAD_MISSES.ANY
	     (Event 08H, Umask 01H) Counts all load misses that	cause a	page
	     walk

     DTLB_LOAD_MISSES.WALK_COMPLETED
	     (Event 08H, Umask 02H) Counts number of completed page walks due
	     to	load miss in the STLB.

     DTLB_LOAD_MISSES.STLB_HIT
	     (Event 08H, Umask 10H) Number of cache load STLB hits

     DTLB_LOAD_MISSES.PDE_MISS
	     (Event 08H, Umask 20H) Number of DTLB cache load misses where the
	     low part of the linear to physical	address	translation was
	     missed.

     DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED
	     (Event 08H, Umask 80H) Counts number of completed large page
	     walks due to load miss in the STLB.

     MEM_INST_RETIRED.LOADS
	     (Event 0BH, Umask 01H) Counts the number of instructions with an
	     architecturally-visible store retired on the architected path.
	     In	conjunction with ld_lat	facility

     MEM_INST_RETIRED.STORES
	     (Event 0BH, Umask 02H) Counts the number of instructions with an
	     architecturally-visible store retired on the architected path.
	     In	conjunction with ld_lat	facility

     MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD
	     (Event 0BH, Umask 10H) Counts the number of instructions exceed-
	     ing the latency specified with ld_lat facility.  In conjunction
	     with ld_lat facility

     MEM_STORE_RETIRED.DTLB_MISS
	     (Event 0CH, Umask 01H) The	event counts the number	of retired
	     stores that missed	the DTLB. The DTLB miss	is not counted if the
	     store operation causes a fault. Does not counter prefetches.
	     Counts both primary and secondary misses to the TLB

     UOPS_ISSUED.ANY
	     (Event 0EH, Umask 01H) Counts the number of Uops issued by	the
	     Register Allocation Table to the Reservation Station, i.e.	the
	     UOPs issued from the front	end to the back	end.

     UOPS_ISSUED.STALLED_CYCLES
	     (Event 0EH, Umask 01H) Counts the number of cycles	no Uops	issued
	     by	the Register Allocation	Table to the Reservation Station, i.e.
	     the UOPs issued from the front end	to the back end.  set
	     invert=1, cmask = 1

     UOPS_ISSUED.FUSED
	     (Event 0EH, Umask 02H) Counts the number of fused Uops that were
	     issued from the Register Allocation Table to the Reservation Sta-
	     tion.

     MEM_UNCORE_RETIRED.L3_DATA_MISS_UNKNOWN
	     (Event 0FH, Umask 01H) Counts number of memory load instructions
	     retired where the memory reference	missed L3 and data source is
	     unknown.  Available only for CPUID	signature 06_2EH

     MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM
	     (Event 0FH, Umask 02H) Counts number of memory load instructions
	     retired where the memory reference	hit modified data in a sibling
	     core residing on the same socket.

     MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT
	     (Event 0FH, Umask 08H) Counts number of memory load instructions
	     retired where the memory reference	missed the L1, L2 and L3
	     caches and	HIT in a remote	socket's cache.	Only counts locally
	     homed lines.

     MEM_UNCORE_RETIRED.REMOTE_DRAM
	     (Event 0FH, Umask 10H) Counts number of memory load instructions
	     retired where the memory reference	missed the L1, L2 and L3
	     caches and	was remotely homed. This includes both DRAM access and
	     HITM in a remote socket's cache for remotely homed	lines.

     MEM_UNCORE_RETIRED.LOCAL_DRAM
	     (Event 0FH, Umask 20H) Counts number of memory load instructions
	     retired where the memory reference	missed the L1, L2 and L3
	     caches and	required a local socket	memory reference. This
	     includes locally homed cachelines that were in a modified state
	     in	another	socket.

     MEM_UNCORE_RETIRED.UNCACHEABLE
	     (Event 0FH, Umask 80H) Counts number of memory load instructions
	     retired where the memory reference	missed the L1, L2 and L3
	     caches and	to perform I/O.	 Available only	for CPUID signature
	     06_2EH

     FP_COMP_OPS_EXE.X87
	     (Event 10H, Umask 01H) Counts the number of FP Computational Uops
	     Executed. The number of FADD, FSUB, FCOM, FMULs, integer MULsand
	     IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event
	     does not distinguish an FADD used in the middle of	a transcenden-
	     tal flow from a separate FADD instruction.

     FP_COMP_OPS_EXE.MMX
	     (Event 10H, Umask 02H) Counts number of MMX Uops executed.

     FP_COMP_OPS_EXE.SSE_FP
	     (Event 10H, Umask 04H) Counts number of SSE and SSE2 FP uops exe-
	     cuted.

     FP_COMP_OPS_EXE.SSE2_INTEGER
	     (Event 10H, Umask 08H) Counts number of SSE2 integer uops exe-
	     cuted.

     FP_COMP_OPS_EXE.SSE_FP_PACKED
	     (Event 10H, Umask 10H) Counts number of SSE FP packed uops	exe-
	     cuted.

     FP_COMP_OPS_EXE.SSE_FP_SCALAR
	     (Event 10H, Umask 20H) Counts number of SSE FP scalar uops	exe-
	     cuted.

     FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION
	     (Event 10H, Umask 40H) Counts number of SSE* FP single precision
	     uops executed.

     FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION
	     (Event 10H, Umask 80H) Counts number of SSE* FP double precision
	     uops executed.

     SIMD_INT_128.PACKED_MPY
	     (Event 12H, Umask 01H) Counts number of 128 bit SIMD integer mul-
	     tiply operations.

     SIMD_INT_128.PACKED_SHIFT
	     (Event 12H, Umask 02H) Counts number of 128 bit SIMD integer
	     shift operations.

     SIMD_INT_128.PACK
	     (Event 12H, Umask 04H) Counts number of 128 bit SIMD integer pack
	     operations.

     SIMD_INT_128.UNPACK
	     (Event 12H, Umask 08H) Counts number of 128 bit SIMD integer
	     unpack operations.

     SIMD_INT_128.PACKED_LOGICAL
	     (Event 12H, Umask 10H) Counts number of 128 bit SIMD integer log-
	     ical operations.

     SIMD_INT_128.PACKED_ARITH
	     (Event 12H, Umask 20H) Counts number of 128 bit SIMD integer
	     arithmetic	operations.

     SIMD_INT_128.SHUFFLE_MOVE
	     (Event 12H, Umask 40H) Counts number of 128 bit SIMD integer
	     shuffle and move operations.

     LOAD_DISPATCH.RS
	     (Event 13H, Umask 01H) Counts number of loads dispatched from the
	     Reservation Station that bypass the Memory	Order Buffer.

     LOAD_DISPATCH.RS_DELAYED
	     (Event 13H, Umask 02H) Counts the number of delayed RS dispatches
	     at	the stage latch. If an RS dispatch can not bypass to LB, it
	     has another chance	to dispatch from the one-cycle delayed staging
	     latch before it is	written	into the LB.

     LOAD_DISPATCH.MOB
	     (Event 13H, Umask 04H) Counts the number of loads dispatched from
	     the Reservation Station to	the Memory Order Buffer.

     LOAD_DISPATCH.ANY
	     (Event 13H, Umask 07H) Counts all loads dispatched	from the
	     Reservation Station.

     ARITH.CYCLES_DIV_BUSY
	     (Event 14H, Umask 01H) Counts the number of cycles	the divider is
	     busy executing divide or square root operations. The divide can
	     be	integer, X87 or	Streaming SIMD Extensions (SSE). The square
	     root operation can	be either X87 or SSE.  Set 'edge =1, invert=1,
	     cmask=1' to count the number of divides.  Count may be incorrect
	     When SMT is on.

     ARITH.MUL
	     (Event 14H, Umask 02H) Counts the number of multiply operations
	     executed. This includes integer as	well as	floating point multi-
	     ply operations but	excludes DPPS mul and MPSAD.  Count may	be
	     incorrect When SMT	is on

     INST_QUEUE_WRITES
	     (Event 17H, Umask 01H) Counts the number of instructions written
	     into the instruction queue	every cycle.

     INST_DECODED.DEC0
	     (Event 18H, Umask 01H) Counts number of instructions that require
	     decoder 0 to be decoded. Usually, this means that the instruction
	     maps to more than 1 uop

     TWO_UOP_INSTS_DECODED
	     (Event 19H, Umask 01H) An instruction that	generates two uops was
	     decoded

     INST_QUEUE_WRITE_CYCLES
	     (Event 1EH, Umask 01H) This event counts the number of cycles
	     during which instructions are written to the instruction queue.
	     Dividing this counter by the number of instructions written to
	     the instruction queue (INST_QUEUE_WRITES) yields the average num-
	     ber of instructions decoded each cycle. If	this number is less
	     than four and the pipe stalls, this indicates that	the decoder is
	     failing to	decode enough instructions per cycle to	sustain	the
	     4-wide pipeline.  If SSE* instructions that are 6 bytes or	longer
	     arrive one	after another, then front end throughput may limit
	     execution speed. In such case,

     LSD_OVERFLOW
	     (Event 20H, Umask 01H) Counts number of loops that	cant stream
	     from the instruction queue.

     L2_RQSTS.LD_HIT
	     (Event 24H, Umask 01H) Counts number of loads that	hit the	L2
	     cache. L2 loads include both L1D demand misses as well as L1D
	     prefetches. L2 loads can be rejected for various reasons. Only
	     non rejected loads	are counted.

     L2_RQSTS.LD_MISS
	     (Event 24H, Umask 02H) Counts the number of loads that miss the
	     L2	cache. L2 loads	include	both L1D demand	misses as well as L1D
	     prefetches.

     L2_RQSTS.LOADS
	     (Event 24H, Umask 03H) Counts all L2 load requests. L2 loads
	     include both L1D demand misses as well as L1D prefetches.

     L2_RQSTS.RFO_HIT
	     (Event 24H, Umask 04H) Counts the number of store RFO requests
	     that hit the L2 cache. L2 RFO requests include both L1D demand
	     RFO misses	as well	as L1D RFO prefetches.	Count includes WC mem-
	     ory requests, where the data is not fetched but the permission to
	     write the line is required.

     L2_RQSTS.RFO_MISS
	     (Event 24H, Umask 08H) Counts the number of store RFO requests
	     that miss the L2 cache. L2	RFO requests include both L1D demand
	     RFO misses	as well	as L1D RFO prefetches.

     L2_RQSTS.RFOS
	     (Event 24H, Umask 0CH) Counts all L2 store	RFO requests. L2 RFO
	     requests include both L1D demand RFO misses as well as L1D	RFO
	     prefetches.

     L2_RQSTS.IFETCH_HIT
	     (Event 24H, Umask 10H) Counts number of instruction fetches that
	     hit the L2	cache. L2 instruction fetches include both L1I demand
	     misses as well as L1I instruction prefetches.

     L2_RQSTS.IFETCH_MISS
	     (Event 24H, Umask 20H) Counts number of instruction fetches that
	     miss the L2 cache.	L2 instruction fetches include both L1I	demand
	     misses as well as L1I instruction prefetches.

     L2_RQSTS.IFETCHES
	     (Event 24H, Umask 30H) Counts all instruction fetches. L2
	     instruction fetches include both L1I demand misses	as well	as L1I
	     instruction prefetches.

     L2_RQSTS.PREFETCH_HIT
	     (Event 24H, Umask 40H) Counts L2 prefetch hits for	both code and
	     data.

     L2_RQSTS.PREFETCH_MISS
	     (Event 24H, Umask 80H) Counts L2 prefetch misses for both code
	     and data.

     L2_RQSTS.PREFETCHES
	     (Event 24H, Umask C0H) Counts all L2 prefetches for both code and
	     data.

     L2_RQSTS.MISS
	     (Event 24H, Umask AAH) Counts all L2 misses for both code and
	     data.

     L2_RQSTS.REFERENCES
	     (Event 24H, Umask FFH) Counts all L2 requests for both code and
	     data.

     L2_DATA_RQSTS.DEMAND.I_STATE
	     (Event 26H, Umask 01H) Counts number of L2	data demand loads
	     where the cache line to be	loaded is in the I (invalid) state,
	     i.e. a cache miss.	L2 demand loads	are both L1D demand misses and
	     L1D prefetches.

     L2_DATA_RQSTS.DEMAND.S_STATE
	     (Event 26H, Umask 02H) Counts number of L2	data demand loads
	     where the cache line to be	loaded is in the S (shared) state. L2
	     demand loads are both L1D demand misses and L1D prefetches.

     L2_DATA_RQSTS.DEMAND.E_STATE
	     (Event 26H, Umask 04H) Counts number of L2	data demand loads
	     where the cache line to be	loaded is in the E (exclusive) state.
	     L2	demand loads are both L1D demand misses	and L1D	prefetches.

     L2_DATA_RQSTS.DEMAND.M_STATE
	     (Event 26H, Umask 08H) Counts number of L2	data demand loads
	     where the cache line to be	loaded is in the M (modified) state.
	     L2	demand loads are both L1D demand misses	and L1D	prefetches.

     L2_DATA_RQSTS.DEMAND.MESI
	     (Event 26H, Umask 0FH) Counts all L2 data demand requests.	L2
	     demand loads are both L1D demand misses and L1D prefetches.

     L2_DATA_RQSTS.PREFETCH.I_STATE
	     (Event 26H, Umask 10H) Counts number of L2	prefetch data loads
	     where the cache line to be	loaded is in the I (invalid) state,
	     i.e. a cache miss.

     L2_DATA_RQSTS.PREFETCH.S_STATE
	     (Event 26H, Umask 20H) Counts number of L2	prefetch data loads
	     where the cache line to be	loaded is in the S (shared) state. A
	     prefetch RFO will miss on an S state line,	while a	prefetch read
	     will hit on an S state line.

     L2_DATA_RQSTS.PREFETCH.E_STATE
	     (Event 26H, Umask 40H) Counts number of L2	prefetch data loads
	     where the cache line to be	loaded is in the E (exclusive) state.

     L2_DATA_RQSTS.PREFETCH.M_STATE
	     (Event 26H, Umask 80H) Counts number of L2	prefetch data loads
	     where the cache line to be	loaded is in the M (modified) state.

     L2_DATA_RQSTS.PREFETCH.MESI
	     (Event 26H, Umask F0H) Counts all L2 prefetch requests.

     L2_DATA_RQSTS.ANY
	     (Event 26H, Umask FFH) Counts all L2 data requests.

     L2_WRITE.RFO.I_STATE
	     (Event 27H, Umask 01H) Counts number of L2	demand store RFO
	     requests where the	cache line to be loaded	is in the I (invalid)
	     state, i.e, a cache miss. The L1D prefetcher does not issue a RFO
	     prefetch.	This is	a demand RFO request

     L2_WRITE.RFO.S_STATE
	     (Event 27H, Umask 02H) Counts number of L2	store RFO requests
	     where the cache line to be	loaded is in the S (shared) state. The
	     L1D prefetcher does not issue a RFO prefetch,.  This is a demand
	     RFO request

     L2_WRITE.RFO.M_STATE
	     (Event 27H, Umask 08H) Counts number of L2	store RFO requests
	     where the cache line to be	loaded is in the M (modified) state.
	     The L1D prefetcher	does not issue a RFO prefetch.	This is	a
	     demand RFO	request

     L2_WRITE.RFO.HIT
	     (Event 27H, Umask 0EH) Counts number of L2	store RFO requests
	     where the cache line to be	loaded is in either the	S, E or	M
	     states. The L1D prefetcher	does not issue a RFO prefetch.	This
	     is	a demand RFO request

     L2_WRITE.RFO.MESI
	     (Event 27H, Umask 0FH) Counts all L2 store	RFO requests.The L1D
	     prefetcher	does not issue a RFO prefetch.	This is	a demand RFO
	     request

     L2_WRITE.LOCK.I_STATE
	     (Event 27H, Umask 10H) Counts number of L2	demand lock RFO
	     requests where the	cache line to be loaded	is in the I (invalid)
	     state, i.e. a cache miss.

     L2_WRITE.LOCK.S_STATE
	     (Event 27H, Umask 20H) Counts number of L2	lock RFO requests
	     where the cache line to be	loaded is in the S (shared) state.

     L2_WRITE.LOCK.E_STATE
	     (Event 27H, Umask 40H) Counts number of L2	demand lock RFO
	     requests where the	cache line to be loaded	is in the E (exclu-
	     sive) state.

     L2_WRITE.LOCK.M_STATE
	     (Event 27H, Umask 80H) Counts number of L2	demand lock RFO
	     requests where the	cache line to be loaded	is in the M (modified)
	     state.

     L2_WRITE.LOCK.HIT
	     (Event 27H, Umask E0H) Counts number of L2	demand lock RFO
	     requests where the	cache line to be loaded	is in either the S, E,
	     or	M state.

     L2_WRITE.LOCK.MESI
	     (Event 27H, Umask F0H) Counts all L2 demand lock RFO requests.

     L1D_WB_L2.I_STATE
	     (Event 28H, Umask 01H) Counts number of L1	writebacks to the L2
	     where the cache line to be	written	is in the I (invalid) state,
	     i.e. a cache miss.

     L1D_WB_L2.S_STATE
	     (Event 28H, Umask 02H) Counts number of L1	writebacks to the L2
	     where the cache line to be	written	is in the S state.

     L1D_WB_L2.E_STATE
	     (Event 28H, Umask 04H) Counts number of L1	writebacks to the L2
	     where the cache line to be	written	is in the E (exclusive)	state.

     L1D_WB_L2.M_STATE
	     (Event 28H, Umask 08H) Counts number of L1	writebacks to the L2
	     where the cache line to be	written	is in the M (modified) state.

     L1D_WB_L2.MESI
	     (Event 28H, Umask 0FH) Counts all L1 writebacks to	the L2.

     L3_LAT_CACHE.REFERENCE
	     (Event 2EH, Umask 4FH) This event counts requests originating
	     from the core that	reference a cache line in the last level
	     cache. The	event count includes speculative traffic but excludes
	     cache line	fills due to a L2 hardware-prefetch. Because cache
	     hierarchy,	cache sizes and	other implementation-specific charac-
	     teristics;	value comparison to estimate performance differences
	     is	not recommended.  see Table A-1

     L3_LAT_CACHE.MISS
	     (Event 2EH, Umask 41H) This event counts each cache miss condi-
	     tion for references to the	last level cache. The event count may
	     include speculative traffic but excludes cache line fills due to
	     L2	hardware-prefetches. Because cache hierarchy, cache sizes and
	     other implementation-specific characteristics; value comparison
	     to	estimate performance differences is not	recommended.  see Ta-
	     ble A-1

     CPU_CLK_UNHALTED.THREAD_P
	     (Event 3CH, Umask 00H) Counts the number of thread	cycles while
	     the thread	is not in a halt state.	 The thread enters the halt
	     state when	it is running the HLT instruction. The core frequency
	     may change	from time to time due to power or thermal throttling.
	     see Table A-1

     CPU_CLK_UNHALTED.REF_P
	     (Event 3CH, Umask 01H) Increments at the frequency	of TSC when
	     not halted.  see Table A-1

     L1D_CACHE_LD.I_STATE
	     (Event 40H, Umask 01H) Counts L1 data cache read requests where
	     the cache line to be loaded is in the I (invalid) state, i.e. the
	     read request missed the cache.  Counter 0,	1 only

     L1D_CACHE_LD.S_STATE
	     (Event 40H, Umask 02H) Counts L1 data cache read requests where
	     the cache line to be loaded is in the S (shared) state.  Counter
	     0,	1 only

     L1D_CACHE_LD.E_STATE
	     (Event 40H, Umask 04H) Counts L1 data cache read requests where
	     the cache line to be loaded is in the E (exclusive) state.
	     Counter 0,	1 only

     L1D_CACHE_LD.M_STATE
	     (Event 40H, Umask 08H) Counts L1 data cache read requests where
	     the cache line to be loaded is in the M (modified)	state.
	     Counter 0,	1 only

     L1D_CACHE_LD.MESI
	     (Event 40H, Umask 0FH) Counts L1 data cache read requests.
	     Counter 0,	1 only

     L1D_CACHE_ST.S_STATE
	     (Event 41H, Umask 02H) Counts L1 data cache store RFO requests
	     where the cache line to be	loaded is in the S (shared) state.
	     Counter 0,	1 only

     L1D_CACHE_ST.E_STATE
	     (Event 41H, Umask 04H) Counts L1 data cache store RFO requests
	     where the cache line to be	loaded is in the E (exclusive) state.
	     Counter 0,	1 only

     L1D_CACHE_ST.M_STATE
	     (Event 41H, Umask 08H) Counts L1 data cache store RFO requests
	     where cache line to be loaded is in the M (modified) state.
	     Counter 0,	1 only

     L1D_CACHE_LOCK.HIT
	     (Event 42H, Umask 01H) Counts retired load	locks that hit in the
	     L1	data cache or hit in an	already	allocated fill buffer. The
	     lock portion of the load lock transaction must hit	in the L1D.
	     The initial load will pull	the lock into the L1 data cache.
	     Counter 0,	1 only

     L1D_CACHE_LOCK.S_STATE
	     (Event 42H, Umask 02H) Counts L1 data cache retired load locks
	     that hit the target cache line in the shared state.  Counter 0, 1
	     only

     L1D_CACHE_LOCK.E_STATE
	     (Event 42H, Umask 04H) Counts L1 data cache retired load locks
	     that hit the target cache line in the exclusive state.  Counter
	     0,	1 only

     L1D_CACHE_LOCK.M_STATE
	     (Event 42H, Umask 08H) Counts L1 data cache retired load locks
	     that hit the target cache line in the modified state.  Counter 0,
	     1 only

     L1D_ALL_REF.ANY
	     (Event 43H, Umask 01H) Counts all references (uncached, specu-
	     lated and retired)	to the L1 data cache, including	all loads and
	     stores with any memory types. The event counts memory accesses
	     only when they are	actually performed. For	example, a load
	     blocked by	unknown	store address and later	performed is only
	     counted once.  The	event does not include non- memory accesses,
	     such as I/O accesses.  Counter 0, 1 only

     L1D_ALL_REF.CACHEABLE
	     (Event 43H, Umask 02H) Counts all data reads and writes (specu-
	     lated and retired)	from cacheable memory, including locked	opera-
	     tions.  Counter 0,	1 only

     DTLB_MISSES.ANY
	     (Event 49H, Umask 01H) Counts the number of misses	in the STLB
	     which causes a page walk.

     DTLB_MISSES.WALK_COMPLETED
	     (Event 49H, Umask 02H) Counts number of misses in the STLB	which
	     resulted in a completed page walk.

     DTLB_MISSES.STLB_HIT
	     (Event 49H, Umask 10H) Counts the number of DTLB first level
	     misses that hit in	the second level TLB. This event is only rele-
	     vant if the core contains multiple	DTLB levels.

     DTLB_MISSES.PDE_MISS
	     (Event 49H, Umask 20H) Number of DTLB misses caused by low	part
	     of	address, includes references to	2M pages because 2M pages do
	     not use the PDE.

     DTLB_MISSES.LARGE_WALK_COMPLETED
	     (Event 49H, Umask 80H) Counts number of misses in the STLB	which
	     resulted in a completed page walk for large pages.

     LOAD_HIT_PRE
	     (Event 4CH, Umask 01H) Counts load	operations sent	to the L1 data
	     cache while a previous SSE	prefetch instruction to	the same cache
	     line has started prefetching but has not yet finished.

     L1D_PREFETCH.REQUESTS
	     (Event 4EH, Umask 01H) Counts number of hardware prefetch
	     requests dispatched out of	the prefetch FIFO.

     L1D_PREFETCH.MISS
	     (Event 4EH, Umask 02H) Counts number of hardware prefetch
	     requests that miss	the L1D. There are two prefetchers in the L1D.
	     A streamer, which predicts	lines sequentially after this one
	     should be fetched,	and the	IP prefetcher that remembers access
	     patterns for the current instruction. The streamer	prefetcher
	     stops on an L1D hit, while	the IP prefetcher does not.

     L1D_PREFETCH.TRIGGERS
	     (Event 4EH, Umask 04H) Counts number of prefetch requests trig-
	     gered by the Finite State Machine and pushed into the prefetch
	     FIFO. Some	of the prefetch	requests are dropped due to overwrites
	     or	competition between the	IP index prefetcher and	streamer
	     prefetcher. The prefetch FIFO contains 4 entries.

     L1D.REPL
	     (Event 51H, Umask 01H) Counts the number of lines brought into
	     the L1 data cache.	 Counter 0, 1 only

     L1D.M_REPL
	     (Event 51H, Umask 02H) Counts the number of modified lines
	     brought into the L1 data cache.  Counter 0, 1 only

     L1D.M_EVICT
	     (Event 51H, Umask 04H) Counts the number of modified lines
	     evicted from the L1 data cache due	to replacement.	 Counter 0, 1
	     only

     L1D.M_SNOOP_EVICT
	     (Event 51H, Umask 08H) Counts the number of modified lines
	     evicted from the L1 data cache due	to snoop HITM intervention.
	     Counter 0,	1 only

     L1D_CACHE_PREFETCH_LOCK_FB_HIT
	     (Event 52H, Umask 01H) Counts the number of cacheable load	lock
	     speculated	instructions accepted into the fill buffer.

     L1D_CACHE_LOCK_FB_HIT
	     (Event 53H, Umask 01H) Counts the number of cacheable load	lock
	     speculated	or retired instructions	accepted into the fill buffer.

     CACHE_LOCK_CYCLES.L1D_L2
	     (Event 63H, Umask 01H) Cycle count	during which the L1D and L2
	     are locked. A lock	is asserted when there is a locked memory
	     access, due to uncacheable	memory,	a locked operation that	spans
	     two cache lines, or a page	walk from an uncacheable page table.
	     Counter 0,	1 only.	L1D and	L2 locks have a	very high performance
	     penalty and it is highly recommended to avoid such	accesses.

     CACHE_LOCK_CYCLES.L1D
	     (Event 63H, Umask 02H) Counts the number of cycles	that cacheline
	     in	the L1 data cache unit is locked.  Counter 0, 1	only.

     IO_TRANSACTIONS
	     (Event 6CH, Umask 01H) Counts the number of completed I/O trans-
	     actions.

     L1I.HITS
	     (Event 80H, Umask 01H) Counts all instruction fetches that	hit
	     the L1 instruction	cache.

     L1I.MISSES
	     (Event 80H, Umask 02H) Counts all instruction fetches that	miss
	     the L1I cache. This includes instruction cache misses, streaming
	     buffer misses, victim cache misses	and uncacheable	fetches. An
	     instruction fetch miss is counted only once and not once for
	     every cycle it is outstanding.

     L1I.READS
	     (Event 80H, Umask 03H) Counts all instruction fetches, including
	     uncacheable fetches that bypass the L1I.

     L1I.CYCLES_STALLED
	     (Event 80H, Umask 04H) Cycle counts for which an instruction
	     fetch stalls due to a L1I cache miss, ITLB	miss or	ITLB fault.

     LARGE_ITLB.HIT
	     (Event 82H, Umask 01H) Counts number of large ITLB	hits.

     ITLB_MISSES.ANY
	     (Event 85H, Umask 01H) Counts the number of misses	in all levels
	     of	the ITLB which causes a	page walk.

     ITLB_MISSES.WALK_COMPLETED
	     (Event 85H, Umask 02H) Counts number of misses in all levels of
	     the ITLB which resulted in	a completed page walk.

     ILD_STALL.LCP
	     (Event 87H, Umask 01H) Cycles Instruction Length Decoder stalls
	     due to length changing prefixes: 66, 67 or	REX.W (for EM64T)
	     instructions which	change the length of the decoded instruction.

     ILD_STALL.MRU
	     (Event 87H, Umask 02H) Instruction	Length Decoder stall cycles
	     due to Brand Prediction Unit (PBU)	Most Recently Used (MRU)
	     bypass.

     ILD_STALL.IQ_FULL
	     (Event 87H, Umask 04H) Stall cycles due to	a full instruction
	     queue.

     ILD_STALL.REGEN
	     (Event 87H, Umask 08H) Counts the number of regen stalls.

     ILD_STALL.ANY
	     (Event 87H, Umask 0FH) Counts any cycles the Instruction Length
	     Decoder is	stalled.

     BR_INST_EXEC.COND
	     (Event 88H, Umask 01H) Counts the number of conditional near
	     branch instructions executed, but not necessarily retired.

     BR_INST_EXEC.DIRECT
	     (Event 88H, Umask 02H) Counts all unconditional near branch
	     instructions excluding calls and indirect branches.

     BR_INST_EXEC.INDIRECT_NON_CALL
	     (Event 88H, Umask 04H) Counts the number of executed indirect
	     near branch instructions that are not calls.

     BR_INST_EXEC.NON_CALLS
	     (Event 88H, Umask 07H) Counts all non call	near branch instruc-
	     tions executed, but not necessarily retired.

     BR_INST_EXEC.RETURN_NEAR
	     (Event 88H, Umask 08H) Counts indirect near branches that have a
	     return mnemonic.

     BR_INST_EXEC.DIRECT_NEAR_CALL
	     (Event 88H, Umask 10H) Counts unconditional near call branch
	     instructions, excluding non call branch, executed.

     BR_INST_EXEC.INDIRECT_NEAR_CALL
	     (Event 88H, Umask 20H) Counts indirect near calls,	including both
	     register and memory indirect, executed.

     BR_INST_EXEC.NEAR_CALLS
	     (Event 88H, Umask 30H) Counts all near call branches executed,
	     but not necessarily retired.

     BR_INST_EXEC.TAKEN
	     (Event 88H, Umask 40H) Counts taken near branches executed, but
	     not necessarily retired.

     BR_INST_EXEC.ANY
	     (Event 88H, Umask 7FH) Counts all near executed branches (not
	     necessarily retired). This	includes only instructions and not
	     micro-op branches.	Frequent branching is not necessarily a	major
	     performance issue.	However	frequent branch	mispredictions may be
	     a problem.

     BR_MISP_EXEC.COND
	     (Event 89H, Umask 01H) Counts the number of mispredicted condi-
	     tional near branch	instructions executed, but not necessarily
	     retired.

     BR_MISP_EXEC.DIRECT
	     (Event 89H, Umask 02H) Counts mispredicted	macro unconditional
	     near branch instructions, excluding calls and indirect branches
	     (should always be 0).

     BR_MISP_EXEC.INDIRECT_NON_CALL
	     (Event 89H, Umask 04H) Counts the number of executed mispredicted
	     indirect near branch instructions that are	not calls.

     BR_MISP_EXEC.NON_CALLS
	     (Event 89H, Umask 07H) Counts mispredicted	non call near branches
	     executed, but not necessarily retired.

     BR_MISP_EXEC.RETURN_NEAR
	     (Event 89H, Umask 08H) Counts mispredicted	indirect branches that
	     have a rear return	mnemonic.

     BR_MISP_EXEC.DIRECT_NEAR_CALL
	     (Event 89H, Umask 10H) Counts mispredicted	non-indirect near
	     calls executed, (should always be 0).

     BR_MISP_EXEC.INDIRECT_NEAR_CALL
	     (Event 89H, Umask 20H) Counts mispredicted	indirect near calls
	     executed, including both register and memory indirect.

     BR_MISP_EXEC.NEAR_CALLS
	     (Event 89H, Umask 30H) Counts all mispredicted near call branches
	     executed, but not necessarily retired.

     BR_MISP_EXEC.TAKEN
	     (Event 89H, Umask 40H) Counts executed mispredicted near branches
	     that are taken, but not necessarily retired.

     BR_MISP_EXEC.ANY
	     (Event 89H, Umask 7FH) Counts the number of mispredicted near
	     branch instructions that were executed, but not necessarily
	     retired.

     RESOURCE_STALLS.ANY
	     (Event A2H, Umask 01H) Counts the number of Allocator resource
	     related stalls. Includes register renaming	buffer entries,	memory
	     buffer entries. In	addition to resource related stalls, this
	     event counts some other events. Includes stalls arising during
	     branch misprediction recovery, such as if retirement of the mis-
	     predicted branch is delayed and stalls arising while store	buffer
	     is	draining from synchronizing operations.	 Does not include
	     stalls due	to SuperQ (off core) queue full, too many cache
	     misses, etc.

     RESOURCE_STALLS.LOAD
	     (Event A2H, Umask 02H) Counts the cycles of stall due to lack of
	     load buffer for load operation.

     RESOURCE_STALLS.RS_FULL
	     (Event A2H, Umask 04H) This event counts the number of cycles
	     when the number of	instructions in	the pipeline waiting for exe-
	     cution reaches the	limit the processor can	handle.	A high count
	     of	this event indicates that there	are long latency operations in
	     the pipe (possibly	load and store operations that miss the	L2
	     cache, or instructions dependent upon instructions	further	down
	     the pipeline that have yet	to retire.  When RS is full, new
	     instructions can not enter	the reservation	station	and start exe-
	     cution.

     RESOURCE_STALLS.STORE
	     (Event A2H, Umask 08H) This event counts the number of cycles
	     that a resource related stall will	occur due to the number	of
	     store instructions	reaching the limit of the pipeline, (i.e. all
	     store buffers are used). The stall	ends when a store instruction
	     commits its data to the cache or memory.

     RESOURCE_STALLS.ROB_FULL
	     (Event A2H, Umask 10H) Counts the cycles of stall due to re-
	     order buffer full.

     RESOURCE_STALLS.FPCW
	     (Event A2H, Umask 20H) Counts the number of cycles	while execu-
	     tion was stalled due to writing the floating-point	unit (FPU)
	     control word.

     RESOURCE_STALLS.MXCSR
	     (Event A2H, Umask 40H) Stalls due to the MXCSR register rename
	     occurring to close	to a previous MXCSR rename. The	MXCSR provides
	     control and status	for the	MMX registers.

     RESOURCE_STALLS.OTHER
	     (Event A2H, Umask 80H) Counts the number of cycles	while execu-
	     tion was stalled due to other resource issues.

     MACRO_INSTS.FUSIONS_DECODED
	     (Event A6H, Umask 01H) Counts the number of instructions decoded
	     that are macro-fused but not necessarily executed or retired.

     BACLEAR_FORCE_IQ
	     (Event A7H, Umask 01H) Counts number of times a BACLEAR was
	     forced by the Instruction Queue. The IQ is	also responsible for
	     providing conditional branch prediction direction based on	a
	     static scheme and dynamic data provided by	the L2 Branch Predic-
	     tion Unit.	If the conditional branch target is not	found in the
	     Target Array and the IQ predicts that the branch is taken,	then
	     the IQ will force the Branch Address Calculator to	issue a
	     BACLEAR. Each BACLEAR asserted by the BAC generates approximately
	     an	8 cycle	bubble in the instruction fetch	pipeline.

     LSD.UOPS
	     (Event A8H, Umask 01H) Counts the number of micro-ops delivered
	     by	loop stream detector Use cmask=1 and invert to count cycles

     ITLB_FLUSH
	     (Event AEH, Umask 01H) Counts the number of ITLB flushes

     OFFCORE_REQUESTS.L1D_WRITEBACK
	     (Event B0H, Umask 40H) Counts number of L1D writebacks to the
	     uncore.

     UOPS_EXECUTED.PORT0
	     (Event B1H, Umask 01H) Counts number of Uops executed that	were
	     issued on port 0. Port 0 handles integer arithmetic, SIMD and FP
	     add Uops.

     UOPS_EXECUTED.PORT1
	     (Event B1H, Umask 02H) Counts number of Uops executed that	were
	     issued on port 1. Port 1 handles integer arithmetic, SIMD,	inte-
	     ger shift,	FP multiply and	FP divide Uops.

     UOPS_EXECUTED.PORT2_CORE
	     (Event B1H, Umask 04H) Counts number of Uops executed that	were
	     issued on port 2. Port 2 handles the load Uops. This is a core
	     count only	and can	not be collected per thread.

     UOPS_EXECUTED.PORT3_CORE
	     (Event B1H, Umask 08H) Counts number of Uops executed that	were
	     issued on port 3. Port 3 handles store Uops. This is a core count
	     only and can not be collected per thread.

     UOPS_EXECUTED.PORT4_CORE
	     (Event B1H, Umask 10H) Counts number of Uops executed that	where
	     issued on port 4. Port 4 handles the value	to be stored for the
	     store Uops	issued on port 3. This is a core count only and	can
	     not be collected per thread.

     UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5
	     (Event B1H, Umask 1FH) Counts cycles when the Uops	executed were
	     issued from any ports except port 5. Use Cmask=1 for active
	     cycles; Cmask=0 for weighted cycles; Use CMask=1, Invert=1	to
	     count P0-4	stalled	cycles Use Cmask=1, Edge=1, Invert=1 to	count
	     P0-4 stalls.

     UOPS_EXECUTED.PORT5
	     (Event B1H, Umask 20H) Counts number of Uops executed that	where
	     issued on port 5.

     UOPS_EXECUTED.CORE_ACTIVE_CYCLES
	     (Event B1H, Umask 3FH) Counts cycles when the Uops	are executing.
	     Use Cmask=1 for active cycles; Cmask=0 for	weighted cycles; Use
	     CMask=1, Invert=1 to count	P0-4 stalled cycles Use	Cmask=1,
	     Edge=1, Invert=1 to count P0-4 stalls.

     UOPS_EXECUTED.PORT015
	     (Event B1H, Umask 40H) Counts number of Uops executed that	where
	     issued on port 0, 1, or 5.	 use cmask=1, invert=1 to count	stall
	     cycles

     UOPS_EXECUTED.PORT234
	     (Event B1H, Umask 80H) Counts number of Uops executed that	where
	     issued on port 2, 3, or 4.

     OFFCORE_REQUESTS_SQ_FULL
	     (Event B2H, Umask 01H) Counts number of cycles the	SQ is full to
	     handle off-core requests.

     OFF_CORE_RESPONSE_0
	     (Event B7H, Umask 01H) see	Section	30.6.1.3, Off-core Response
	     Performance Monitoring in the Processor Core Requires programming
	     MSR 01A6H

     SNOOP_RESPONSE.HIT
	     (Event B8H, Umask 01H) Counts HIT snoop response sent by this
	     thread in response	to a snoop request.

     SNOOP_RESPONSE.HITE
	     (Event B8H, Umask 02H) Counts HIT E snoop response	sent by	this
	     thread in response	to a snoop request.

     SNOOP_RESPONSE.HITM
	     (Event B8H, Umask 04H) Counts HIT M snoop response	sent by	this
	     thread in response	to a snoop request.

     OFF_CORE_RESPONSE_1
	     (Event BBH, Umask 01H) see	Section	30.6.1.3, Off-core Response
	     Performance Monitoring in the Processor Core Requires programming
	     MSR 01A7H

     INST_RETIRED.ANY_P
	     (Event C0H, Umask 01H) See	Table A-1 Notes: INST_RETIRED.ANY is
	     counted by	a designated fixed counter.  INST_RETIRED.ANY_P	is
	     counted by	a programmable counter and is an architectural perfor-
	     mance event. Event	is supported if	CPUID.A.EBX[1] = 0.  Counting:
	     Faulting executions of GETSEC/VM entry/VM Exit/MWait will not
	     count as retired instructions.

     INST_RETIRED.X87
	     (Event C0H, Umask 02H) Counts the number of MMX instructions
	     retired.

     INST_RETIRED.MMX
	     (Event C0H, Umask 04H) Counts the number of floating point	compu-
	     tational operations retired: floating point computational opera-
	     tions executed by the assist handler and sub-operations of	com-
	     plex floating point instructions like transcendental instruc-
	     tions.

     UOPS_RETIRED.ANY
	     (Event C2H, Umask 01H) Counts the number of micro-ops retired,
	     (macro-fused=1, micro- fused=2, others=1; maximum count of	8 per
	     cycle). Most instructions are composed of one or two micro-ops.
	     Some instructions are decoded into	longer sequences such as
	     repeat instructions, floating point transcendental	instructions,
	     and assists.  Use cmask=1 and invert to count active cycles or
	     stalled cycles

     UOPS_RETIRED.RETIRE_SLOTS
	     (Event C2H, Umask 02H) Counts the number of retirement slots used
	     each cycle

     UOPS_RETIRED.MACRO_FUSED
	     (Event C2H, Umask 04H) Counts number of macro-fused uops retired.

     MACHINE_CLEARS.CYCLES
	     (Event C3H, Umask 01H) Counts the cycles machine clear is
	     asserted.

     MACHINE_CLEARS.MEM_ORDER
	     (Event C3H, Umask 02H) Counts the number of machine clears	due to
	     memory order conflicts.

     MACHINE_CLEARS.SMC
	     (Event C3H, Umask 04H) Counts the number of times that a program
	     writes to a code section.	Self-modifying code causes a sever
	     penalty in	all Intel 64 and IA-32 processors. The modified	cache
	     line is written back to the L2 and	L3caches.

     BR_INST_RETIRED.ALL_BRANCHES
	     (Event C4H, Umask 00H) See	Table A-1

     BR_INST_RETIRED.CONDITIONAL
	     (Event C4H, Umask 01H) Counts the number of conditional branch
	     instructions retired.

     BR_INST_RETIRED.NEAR_CALL
	     (Event C4H, Umask 02H) Counts the number of direct	& indirect
	     near unconditional	calls retired

     BR_INST_RETIRED.ALL_BRANCHES
	     (Event C4H, Umask 04H) Counts the number of branch	instructions
	     retired

     BR_MISP_RETIRED.ALL_BRANCHES
	     (Event C5H, Umask 00H) See	Table A-1

     BR_MISP_RETIRED.NEAR_CALL
	     (Event C5H, Umask 02H) Counts mispredicted	direct & indirect near
	     unconditional retired calls.

     SSEX_UOPS_RETIRED.PACKED_SINGLE
	     (Event C7H, Umask 01H) Counts SIMD	packed single-precision	float-
	     ing point Uops retired.

     SSEX_UOPS_RETIRED.SCALAR_SINGLE
	     (Event C7H, Umask 02H) Counts SIMD	calar single-precision float-
	     ing point Uops retired.

     SSEX_UOPS_RETIRED.PACKED_DOUBLE
	     (Event C7H, Umask 04H) Counts SIMD	packed double- precision
	     floating point Uops retired.

     SSEX_UOPS_RETIRED.SCALAR_DOUBLE
	     (Event C7H, Umask 08H) Counts SIMD	scalar double-precision	float-
	     ing point Uops retired.

     SSEX_UOPS_RETIRED.VECTOR_INTEGER
	     (Event C7H, Umask 10H) Counts 128-bit SIMD	vector integer Uops
	     retired.

     ITLB_MISS_RETIRED
	     (Event C8H, Umask 20H) Counts the number of retired instructions
	     that missed the ITLB when the instruction was fetched.

     MEM_LOAD_RETIRED.L1D_HIT
	     (Event CBH, Umask 01H) Counts number of retired loads that	hit
	     the L1 data cache.

     MEM_LOAD_RETIRED.L2_HIT
	     (Event CBH, Umask 02H) Counts number of retired loads that	hit
	     the L2 data cache.

     MEM_LOAD_RETIRED.L3_UNSHARED_HIT
	     (Event CBH, Umask 04H) Counts number of retired loads that	hit
	     their own,	unshared lines in the L3 cache.

     MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM
	     (Event CBH, Umask 08H) Counts number of retired loads that	hit in
	     a sibling core's L2 (on die core).	Since the L3 is	inclusive of
	     all cores on the package, this is an L3 hit. This counts both
	     clean or modified hits.

     MEM_LOAD_RETIRED.L3_MISS
	     (Event CBH, Umask 10H) Counts number of retired loads that	miss
	     the L3 cache. The load was	satisfied by a remote socket, local
	     memory or an IOH.

     MEM_LOAD_RETIRED.HIT_LFB
	     (Event CBH, Umask 40H) Counts number of retired loads that	miss
	     the L1D and the address is	located	in an allocated	line fill buf-
	     fer and will soon be committed to cache. This is counting sec-
	     ondary L1D	misses.

     MEM_LOAD_RETIRED.DTLB_MISS
	     (Event CBH, Umask 80H) Counts the number of retired loads that
	     missed the	DTLB. The DTLB miss is not counted if the load opera-
	     tion causes a fault. This event counts loads from cacheable mem-
	     ory only. The event does not count	loads by software prefetches.
	     Counts both primary and secondary misses to the TLB.

     FP_MMX_TRANS.TO_FP
	     (Event CCH, Umask 01H) Counts the first floating-point instruc-
	     tion following any	MMX instruction.  You can use this event to
	     estimate the penalties for	the transitions	between	floating-point
	     and MMX technology	states.

     FP_MMX_TRANS.TO_MMX
	     (Event CCH, Umask 02H) Counts the first MMX instruction following
	     a floating-point instruction. You can use this event to estimate
	     the penalties for the transitions between floating-point and MMX
	     technology	states.

     FP_MMX_TRANS.ANY
	     (Event CCH, Umask 03H) Counts all transitions from	floating point
	     to	MMX instructions and from MMX instructions to floating point
	     instructions. You can use this event to estimate the penalties
	     for the transitions between floating-point	and MMX	technology
	     states.

     MACRO_INSTS.DECODED
	     (Event D0H, Umask 01H) Counts the number of instructions decoded,
	     (but not necessarily executed or retired).

     UOPS_DECODED.MS
	     (Event D1H, Umask 02H) Counts the number of Uops decoded by the
	     Microcode Sequencer, MS. The MS delivers uops when	the instruc-
	     tion is more than 4 uops long or a	microcode assist is occurring.

     UOPS_DECODED.ESP_FOLDING
	     (Event D1H, Umask 04H) Counts number of stack pointer (ESP)
	     instructions decoded: push	, pop ,	call , ret, etc. ESP instruc-
	     tions do not generate a Uop to increment or decrement ESP.
	     Instead, they update an ESP_Offset	register that keeps track of
	     the delta to the current value of the ESP register.

     UOPS_DECODED.ESP_SYNC
	     (Event D1H, Umask 08H) Counts number of stack pointer (ESP) sync
	     operations	where an ESP instruction is corrected by adding	the
	     ESP offset	register to the	current	value of the ESP register.

     RAT_STALLS.FLAGS
	     (Event D2H, Umask 01H) Counts the number of cycles	during which
	     execution stalled due to several reasons, one of which is a par-
	     tial flag register	stall. A partial register stall	may occur when
	     two conditions are	met: 1)	an instruction modifies	some, but not
	     all, of the flags in the flag register and	2) the next instruc-
	     tion, which depends on flags, depends on flags that were not mod-
	     ified by this instruction.

     RAT_STALLS.REGISTERS
	     (Event D2H, Umask 02H) This event counts the number of cycles
	     instruction execution latency became longer than the defined
	     latency because the instruction used a register that was par-
	     tially written by previous	instruction.

     RAT_STALLS.ROB_READ_PORT
	     (Event D2H, Umask 04H) Counts the number of cycles	when ROB read
	     port stalls occurred, which did not allow new micro-ops to	enter
	     the out-of-order pipeline.	Note that, at this stage in the	pipe-
	     line, additional stalls may occur at the same cycle and prevent
	     the stalled micro-ops from	entering the pipe. In such a case,
	     micro-ops retry entering the execution pipe in the	next cycle and
	     the ROB-read port stall is	counted	again.

     RAT_STALLS.SCOREBOARD
	     (Event D2H, Umask 08H) Counts the cycles where we stall due to
	     microarchitecturally required serialization. Microcode score-
	     boarding stalls.

     RAT_STALLS.ANY
	     (Event D2H, Umask 0FH) Counts all Register	Allocation Table stall
	     cycles due	to: Cycles when	ROB read port stalls occurred, which
	     did not allow new micro-ops to enter the execution	pipe. Cycles
	     when partial register stalls occurred Cycles when flag stalls
	     occurred Cycles floating-point unit (FPU) status word stalls
	     occurred. To count	each of	these conditions separately use	the
	     events: RAT_STALLS.ROB_READ_PORT, RAT_STALLS.PARTIAL,
	     RAT_STALLS.FLAGS, and RAT_STALLS.FPSW.

     SEG_RENAME_STALLS
	     (Event D4H, Umask 01H) Counts the number of stall cycles due to
	     the lack of renaming resources for	the ES,	DS, FS,	and GS segment
	     registers.	If a segment is	renamed	but not	retired	and a second
	     update to the same	segment	occurs,	a stall	occurs in the front-
	     end of the	pipeline until the renamed segment retires.

     ES_REG_RENAMES
	     (Event D5H, Umask 01H) Counts the number of times the ES segment
	     register is renamed.

     UOP_UNFUSION
	     (Event DBH, Umask 01H) Counts unfusion events due to floating
	     point exception to	a fused	uop.

     BR_INST_DECODED
	     (Event E0H, Umask 01H) Counts the number of branch	instructions
	     decoded.

     BPU_MISSED_CALL_RET
	     (Event E5H, Umask 01H) Counts number of times the Branch Predic-
	     tion Unit missed predicting a call	or return branch.

     BACLEAR.CLEAR
	     (Event E6H, Umask 01H) Counts the number of times the front end
	     is	resteered, mainly when the Branch Prediction Unit cannot pro-
	     vide a correct prediction and this	is corrected by	the Branch
	     Address Calculator	at the front end. This can occur if the	code
	     has many branches such that they cannot be	consumed by the	BPU.
	     Each BACLEAR asserted by the BAC generates	approximately an 8
	     cycle bubble in the instruction fetch pipeline. The effect	on
	     total execution time depends on the surrounding code.

     BACLEAR.BAD_TARGET
	     (Event E6H, Umask 02H) Counts number of Branch Address Calculator
	     clears (BACLEAR) asserted due to conditional branch instructions
	     in	which there was	a target hit but the direction was wrong. Each
	     BACLEAR asserted by the BAC generates approximately an 8 cycle
	     bubble in the instruction fetch pipeline.

     BPU_CLEARS.EARLY
	     (Event E8H, Umask 01H) Counts early (normal) Branch Prediction
	     Unit clears: BPU predicted	a taken	branch after incorrectly
	     assuming that it was not taken.  The BPU clear leads to 2 cycle
	     bubble in the Front End.

     BPU_CLEARS.LATE
	     (Event E8H, Umask 02H) Counts late	Branch Prediction Unit clears
	     due to Most Recently Used conflicts. The PBU clear	leads to a 3
	     cycle bubble in the Front End.

     L2_TRANSACTIONS.LOAD
	     (Event F0H, Umask 01H) Counts L2 load operations due to HW
	     prefetch or demand	loads.

     L2_TRANSACTIONS.RFO
	     (Event F0H, Umask 02H) Counts L2 RFO operations due to HW
	     prefetch or demand	RFOs.

     L2_TRANSACTIONS.IFETCH
	     (Event F0H, Umask 04H) Counts L2 instruction fetch	operations due
	     to	HW prefetch or demand ifetch.

     L2_TRANSACTIONS.PREFETCH
	     (Event F0H, Umask 08H) Counts L2 prefetch operations.

     L2_TRANSACTIONS.L1D_WB
	     (Event F0H, Umask 10H) Counts L1D writeback operations to the L2.

     L2_TRANSACTIONS.FILL
	     (Event F0H, Umask 20H) Counts L2 cache line fill operations due
	     to	load, RFO, L1D writeback or prefetch.

     L2_TRANSACTIONS.WB
	     (Event F0H, Umask 40H) Counts L2 writeback	operations to the L3.

     L2_TRANSACTIONS.ANY
	     (Event F0H, Umask 80H) Counts all L2 cache	operations.

     L2_LINES_IN.S_STATE
	     (Event F1H, Umask 02H) Counts the number of cache lines allocated
	     in	the L2 cache in	the S (shared) state.

     L2_LINES_IN.E_STATE
	     (Event F1H, Umask 04H) Counts the number of cache lines allocated
	     in	the L2 cache in	the E (exclusive) state.

     L2_LINES_IN.ANY
	     (Event F1H, Umask 07H) Counts the number of cache lines allocated
	     in	the L2 cache.

     L2_LINES_OUT.DEMAND_CLEAN
	     (Event F2H, Umask 01H) Counts L2 clean cache lines	evicted	by a
	     demand request.

     L2_LINES_OUT.DEMAND_DIRTY
	     (Event F2H, Umask 02H) Counts L2 dirty (modified) cache lines
	     evicted by	a demand request.

     L2_LINES_OUT.PREFETCH_CLEAN
	     (Event F2H, Umask 04H) Counts L2 clean cache line evicted by a
	     prefetch request.

     L2_LINES_OUT.PREFETCH_DIRTY
	     (Event F2H, Umask 08H) Counts L2 modified cache line evicted by a
	     prefetch request.

     L2_LINES_OUT.ANY
	     (Event F2H, Umask 0FH) Counts all L2 cache	lines evicted for any
	     reason.

     SQ_MISC.SPLIT_LOCK
	     (Event F4H, Umask 10H) Counts the number of SQ lock splits	across
	     a cache line.

     SQ_FULL_STALL_CYCLES
	     (Event F6H, Umask 01H) Counts cycles the Super Queue is full.
	     Neither of	the threads on this core will be able to access	the
	     uncore.

     FP_ASSIST.ALL
	     (Event F7H, Umask 01H) Counts the number of floating point	opera-
	     tions executed that required micro-code assist intervention.
	     Assists are required in the following cases: SSE instructions,
	     (Denormal input when the DAZ flag is off or Underflow result when
	     the FTZ flag is off): x87 instructions, (NaN or denormal are
	     loaded to a register or used as input from	memory,	Division by 0
	     or	Underflow output).

     FP_ASSIST.OUTPUT
	     (Event F7H, Umask 02H) Counts number of floating point micro-code
	     assist when the output value (destination register) is invalid.

     FP_ASSIST.INPUT
	     (Event F7H, Umask 04H) Counts number of floating point micro-code
	     assist when the input value (one of the source operands to	an FP
	     instruction) is invalid.

     SIMD_INT_64.PACKED_MPY
	     (Event FDH, Umask 01H) Counts number of SID integer 64 bit	packed
	     multiply operations.

     SIMD_INT_64.PACKED_SHIFT
	     (Event FDH, Umask 02H) Counts number of SID integer 64 bit	packed
	     shift operations.

     SIMD_INT_64.PACK
	     (Event FDH, Umask 04H) Counts number of SID integer 64 bit	pack
	     operations.

     SIMD_INT_64.UNPACK
	     (Event FDH, Umask 08H) Counts number of SID integer 64 bit	unpack
	     operations.

     SIMD_INT_64.PACKED_LOGICAL
	     (Event FDH, Umask 10H) Counts number of SID integer 64 bit	logi-
	     cal operations.

     SIMD_INT_64.PACKED_ARITH
	     (Event FDH, Umask 20H) Counts number of SID integer 64 bit	arith-
	     metic operations.

     SIMD_INT_64.SHUFFLE_MOVE
	     (Event FDH, Umask 40H) Counts number of SID integer 64 bit	shift
	     or	move operations.

   Event Specifiers (Programmable PMCs)
     Core i7 and Xeon 5500 programmable	PMCs support the following events as
     June 2009 document	(removed in December 2009):

     SB_FORWARD.ANY
	     (Event 02H, Umask 01H) Counts the number of store forwards.

     LOAD_BLOCK.STD
	     (Event 03H, Umask 01H) Counts the number of loads blocked by a
	     preceding store with unknown data.

     LOAD_BLOCK.ADDRESS_OFFSET
	     (Event 03H, Umask 04H) Counts the number of loads blocked by a
	     preceding store address.

     LOAD_BLOCK.ADDRESS_OFFSET
	     (Event 01H, Umask 04H) Counts the cycles of store buffer drains.

     MISALIGN_MEM_REF.LOAD
	     (Event 05H, Umask 01H) Counts the number of misaligned load ref-
	     erences

     MISALIGN_MEM_REF.STORE
	     (Event 05H, Umask 02H) Counts the number of misaligned store ref-
	     erences

     MISALIGN_MEM_REF.ANY
	     (Event 05H, Umask 03H) Counts the number of misaligned memory
	     references

     STORE_BLOCKS.NOT_STA
	     (Event 06H, Umask 01H) This event counts the number of load oper-
	     ations delayed caused by preceding	stores whose addresses are
	     known but whose data is unknown, and preceding stores that	con-
	     flict with	the load but which incompletely	overlap	the load.

     STORE_BLOCKS.STA
	     (Event 06H, Umask 02H) This event counts load operations delayed
	     caused by preceding stores	whose addresses	are unknown (STA
	     block).

     STORE_BLOCKS.ANY
	     (Event 06H, Umask 0FH) All	loads delayed due to store blocks

     MEMORY_DISAMBIGURATION.RESET
	     (Event 09H, Umask 01H) Counts memory disambiguration reset	cycles

     MEMORY_DISAMBIGURATION.SUCCESS
	     (Event 09H, Umask 02H) Counts the number of loads that memory
	     disambiguration succeeded

     MEMORY_DISAMBIGURATION.WATCHDOG
	     (Event 09H, Umask 04H) Counts the number of times the memory dis-
	     ambiguration watchdog kicked in.

     MEMORY_DISAMBIGURATION.WATCH_CYCLES
	     (Event 09H, Umask 08H) Counts the cycles that the memory disam-
	     biguration	watchdog is active.  set invert=1, cmask = 1

     HW_INT.RCV
	     (Event 1DH, Umask 01H) Number of interrupt	received

     HW_INT.CYCLES_MASKED
	     (Event 1DH, Umask 02H) Number of cycles interrupt are masked

     HW_INT.CYCLES_PENDING_AND_MASKED
	     (Event 1DH, Umask 04H) Number of cycles interrupts	are pending
	     and masked

     HW_INT.CYCLES_PENDING_AND_MASKED
	     (Event 04H, Umask 04H) Counts number of L2	store RFO requests
	     where the cache line to be	loaded is in the E (exclusive) state.
	     The L1D prefetcher	does not issue a RFO prefetch.	This is	a
	     demand RFO	request

     HW_INT.CYCLES_PENDING_AND_MASKED
	     (Event 27H, Umask 04H) LONGEST_LAT_CACH E.MISS

     UOPS_DECODED.DEC0
	     (Event 3DH, Umask 01H) Counts micro-ops decoded by	decoder	0.

     UOPS_DECODED.DEC0
	     (Event 01H, Umask 01H) Counts L1 data cache store RFO requests
	     where the cache line to be	loaded is in the I state.  Counter 0,
	     1 only

     0FH     (Event 41H, Umask 41H) L1D_CACHE_ST.MESI Counts L1	data cache
	     store RFO requests.  Counter 0, 1 only

     DTLB_MISSES.PDE_MISS
	     (Event 49H, Umask 20H) Number of DTLB cache misses	where the low
	     part of the linear	to physical address translation	was missed.

     DTLB_MISSES.PDP_MISS
	     (Event 49H, Umask 40H) Number of DTLB misses where	the high part
	     of	the linear to physical address translation was missed.

     DTLB_MISSES.LARGE_WALK_COMPLETED
	     (Event 49H, Umask 80H) Counts number of completed large page
	     walks due to misses in the	STLB.

     SSE_MEM_EXEC.NTA
	     (Event 4BH, Umask 01H) Counts number of SSE NTA prefetch/weakly-
	     ordered instructions which	missed the L1 data cache.

     SSE_MEM_EXEC.STREAMING_STORES
	     (Event 4BH, Umask 08H) Counts number of SSE non temporal stores

     SFENCE_CYCLES
	     (Event 4DH, Umask 01H) Counts store fence cycles

     EPT.EPDE_MISS
	     (Event 4FH, Umask 02H) Counts Extended Page Directory Entry
	     misses. The Extended Page Directory cache is used by Virtual
	     Machine operating systems while the guest operating systems use
	     the standard TLB caches.

     EPT.EPDPE_HIT
	     (Event 4FH, Umask 04H) Counts Extended Page Directory Pointer
	     Entry hits.

     EPT.EPDPE_MISS
	     (Event 4FH, Umask 08H) Counts Extended Page Directory Pointer
	     Entry misses. T

     OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA
	     (Event 60H, Umask 01H) Counts weighted cycles of offcore demand
	     data read requests. Does not include L2 prefetch requests.
	     counter 0

     OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE
	     (Event 60H, Umask 02H) Counts weighted cycles of offcore demand
	     code read requests. Does not include L2 prefetch requests.
	     counter 0

     OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO
	     (Event 60H, Umask 04H) Counts weighted cycles of offcore demand
	     RFO requests. Does	not include L2 prefetch	requests.  counter 0

     OFFCORE_REQUESTS_OUTSTANDING.ANY.READ
	     (Event 60H, Umask 08H) Counts weighted cycles of offcore read
	     requests of any kind. Include L2 prefetch requests.  counter 0

     IFU_IVC.FULL
	     (Event 81H, Umask 01H) Instruction	Fetche unit victim cache full.

     IFU_IVC.L1I_EVICTION
	     (Event 81H, Umask 02H) L1 Instruction cache evictions.

     L1I_OPPORTUNISTIC_HITS
	     (Event 83H, Umask 01H) Opportunistic hits in streaming.

     ITLB_MISSES.WALK_CYCLES
	     (Event 85H, Umask 04H) Counts ITLB	miss page walk cycles.

     ITLB_MISSES.PMH_BUSY_CYCLES
	     (Event 85H, Umask 04H) Counts PMH busy cycles.

     ITLB_MISSES.STLB_HIT
	     (Event 85H, Umask 10H) Counts the number of ITLB misses that hit
	     in	the second level TLB.

     ITLB_MISSES.PDE_MISS
	     (Event 85H, Umask 20H) Number of ITLB misses where	the low	part
	     of	the linear to physical address translation was missed.

     ITLB_MISSES.PDP_MISS
	     (Event 85H, Umask 40H) Number of ITLB misses where	the high part
	     of	the linear to physical address translation was missed.

     ITLB_MISSES.LARGE_WALK_COMPLETED
	     (Event 85H, Umask 80H) Counts number of completed large page
	     walks due to misses in the	STLB.

     ITLB_MISSES.LARGE_WALK_COMPLETED
	     (Event 01H, Umask 80H) Counts number of offcore demand data read
	     requests. Does not	count L2 prefetch requests.

     OFFCORE_REQUESTS.DEMAND.READ_CODE
	     (Event B0H, Umask 02H) Counts number of offcore demand code read
	     requests. Does not	count L2 prefetch requests.

     OFFCORE_REQUESTS.DEMAND.RFO
	     (Event B0H, Umask 04H) Counts number of offcore demand RFO
	     requests. Does not	count L2 prefetch requests.

     OFFCORE_REQUESTS.ANY.READ
	     (Event B0H, Umask 08H) Counts number of offcore read requests.
	     Includes L2 prefetch requests.

     OFFCORE_REQUESTS.ANY.RFO
	     (Event B0H, Umask 10H) Counts number of offcore RFO requests.
	     Includes L2 prefetch requests.

     OFFCORE_REQUESTS.UNCACHED_MEM
	     (Event B0H, Umask 20H) Counts number of offcore uncached memory
	     requests.

     OFFCORE_REQUESTS.ANY
	     (Event B0H, Umask 80H) Counts all offcore requests.

     SNOOPQ_REQUESTS_OUTSTANDING.DATA
	     (Event B3H, Umask 01H) Counts weighted cycles of snoopq requests
	     for data. Counter 0 only Use cmask=1 to count cycles not empty.

     SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE
	     (Event B3H, Umask 02H) Counts weighted cycles of snoopq invali-
	     date requests. Counter 0 only Use cmask=1 to count	cycles not
	     empty.

     SNOOPQ_REQUESTS_OUTSTANDING.CODE
	     (Event B3H, Umask 04H) Counts weighted cycles of snoopq requests
	     for code. Counter 0 only Use cmask=1 to count cycles not empty.

     SNOOPQ_REQUESTS_OUTSTANDING.CODE
	     (Event BAH, Umask 04H) Counts number of TPR reads

     PIC_ACCESSES.TPR_WRITES
	     (Event BAH, Umask 02H) Counts number of TPR writes	one or two
	     micro-ops.	Some instructions are decoded into longer sequences

     MACHINE_CLEARS.FUSION_ASSIST
	     (Event C3H, Umask 10H) Counts the number of macro-fusion assists
	     Counts SIMD packed	single-	precision floating point Uops retired.

     BOGUS_BR
	     (Event E4H, Umask 01H) Counts the number of bogus branches.

     L2_HW_PREFETCH.HIT
	     (Event F3H, Umask 01H) Count L2 HW	prefetcher detector hits

     L2_HW_PREFETCH.ALLOC
	     (Event F3H, Umask 02H) Count L2 HW	prefetcher allocations

     L2_HW_PREFETCH.DATA_TRIGGER
	     (Event F3H, Umask 04H) Count L2 HW	data prefetcher	triggered

     L2_HW_PREFETCH.CODE_TRIGGER
	     (Event F3H, Umask 08H) Count L2 HW	code prefetcher	triggered

     L2_HW_PREFETCH.DCA_TRIGGER
	     (Event F3H, Umask 10H) Count L2 HW	DCA prefetcher triggered

     L2_HW_PREFETCH.KICK_START
	     (Event F3H, Umask 20H) Count L2 HW	prefetcher kick	started

     SQ_MISC.PROMOTION
	     (Event F4H, Umask 01H) Counts the number of L2 secondary misses
	     that hit the Super	Queue.

     SQ_MISC.PROMOTION_POST_GO
	     (Event F4H, Umask 02H) Counts the number of L2 secondary misses
	     during the	Super Queue filling L2.

     SQ_MISC.LRU_HINTS
	     (Event F4H, Umask 04H) Counts number of Super Queue LRU hints
	     sent to L3.

     SQ_MISC.FILL_DROPPED
	     (Event F4H, Umask 08H) Counts the number of SQ L2 fills dropped
	     due to L2 busy.

     SEGMENT_REG_LOADS
	     (Event F8H, Umask 01H) Counts number of segment register loads.

SEE ALSO
     pmc(3), pmc.atom(3), pmc.core(3), pmc.corei7uc(3),	pmc.iaf(3), pmc.k7(3),
     pmc.k8(3),	pmc.p4(3), pmc.p5(3), pmc.p6(3), pmc.soft(3), pmc.tsc(3),
     pmc.ucf(3), pmc.westmere(3), pmc.westmereuc(3), pmc_cpuinfo(3),
     pmclog(3),	hwpmc(4)

HISTORY
     The pmc library first appeared in FreeBSD 6.0.

AUTHORS
     The Performance Counters Library (libpmc, -lpmc) library was written by
     Joseph Koshy <jkoshy@FreeBSD.org>.

FreeBSD	Ports 11.2		March 24, 2010		    FreeBSD Ports 11.2

NAME | LIBRARY | SYNOPSIS | DESCRIPTION | SEE ALSO | HISTORY | AUTHORS

Want to link to this manual page? Use this URL:
<https://www.freebsd.org/cgi/man.cgi?query=pmc.corei7&manpath=FreeBSD+12.0-RELEASE+and+Ports>

home | help