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TBLGEN(1)			     LLVM			     TBLGEN(1)

NAME
       tblgen -	Target Description To C++ Code Generator

SYNOPSIS
       tblgen [options]	[filename]

DESCRIPTION
       tblgen  translates  from	 target	 description (.td) files into C++ code
       that can	be included in the definition of an LLVM target	library.  Most
       users  of  LLVM	will not need to use this program.  It is only for as-
       sisting with writing an LLVM target backend.

       The input and output of tblgen is beyond	the scope of this short	intro-
       duction;	please see the introduction to TableGen.

       The  filename argument specifies	the name of a Target Description (.td)
       file to read as input.

OPTIONS
       -help  Print a summary of command line options.

       -o filename
	      Specify the output file name.  If	filename  is  -,  then	tblgen
	      sends its	output to standard output.

       -I directory
	      Specify  where to	find other target description files for	inclu-
	      sion.  The directory value should	be a full or partial path to a
	      directory	that contains target description files.

       -asmparsernum N
	      Make -gen-asm-parser emit	assembly writer	number N.

       -asmwriternum N
	      Make -gen-asm-writer emit	assembly writer	number N.

       -class className
	      Print the	enumeration list for this class.

       -print-records
	      Print all	records	to standard output (default).

       -dump-json
	      Print a JSON representation of all records, suitable for further
	      automated	processing.

       -print-enums
	      Print enumeration	values for a class.

       -print-sets
	      Print expanded sets for testing DAG exprs.

       -gen-emitter
	      Generate machine code emitter.

       -gen-register-info
	      Generate registers and register classes info.

       -gen-instr-info
	      Generate instruction descriptions.

       -gen-asm-writer
	      Generate the assembly writer.

       -gen-disassembler
	      Generate disassembler.

       -gen-pseudo-lowering
	      Generate pseudo instruction lowering.

       -gen-dag-isel
	      Generate a DAG (Directed Acycle Graph) instruction selector.

       -gen-asm-matcher
	      Generate assembly	instruction matcher.

       -gen-dfa-packetizer
	      Generate DFA Packetizer for VLIW targets.

       -gen-fast-isel
	      Generate a "fast"	instruction selector.

       -gen-subtarget
	      Generate subtarget enumerations.

       -gen-intrinsic-enums
	      Generate intrinsic enums.

       -gen-intrinsic-impl
	      Generate intrinsic implementation.

       -gen-tgt-intrinsic
	      Generate target intrinsic	information.

       -gen-enhanced-disassembly-info
	      Generate enhanced	disassembly info.

       -version
	      Show the version number of this program.

EXIT STATUS
       If tblgen succeeds, it will exit	with 0.	 Otherwise, if	an  error  oc-
       curs, it	will exit with a non-zero value.

AUTHOR
       Maintained by The LLVM Team (http://llvm.org/).

COPYRIGHT
       2003-2018, LLVM Project

7				  2018-08-02			     TBLGEN(1)

NAME | SYNOPSIS | DESCRIPTION | OPTIONS | EXIT STATUS | AUTHOR | COPYRIGHT

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