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       cougar -	Hierarchical netlist extractor

       cougar  [  -v  ]	[ -c ] [ -f ] [	-t ] [ -ar ] [ -ac ] input_name	[ out-
       put_name	]

       Lynx changed its	name to	Cougar during May 2002 in order	to avoid  name
       conflict	with the famous	text-mode Web browser.	Cougar is a hierarchi-
       cal layout extractor.  It builds	a netlist of interconnections  from  a
       symbolic	 layout	 view.	The input argument is the name of the symbolic
       layout cell to be extracted, using as input format the one selected  by
       the  MBK_IN_PH(1)  environment variable.	 If output is present, the re-
       sulting netlist will be given this name.	 If no output is  given,  then
       input  will  also  be the generated netlist name.  The output format is
       specified by the	MBK_OUT_LO(1) environment variable.
       As most of the Alliance cad tools, cougar uses mbk(1) environment vari-
       ables.	MBK_CATA_LIB(1), MBK_WORK_LIB(1), MBK_IN_PH(1),	MBK_OUT_LO(1),

       Cougar computes capacitances attached to	the signals if the -ac	option
       is  set.	At the moment, the value of these capacitances is computed for
       a typical one micron technology,	and cannot  be	changed	 by  the  user
       through	a technology file.  The	extracted netlist can be simulated for
       performance evaluation.
       The typical capacitances	are given below	in 10e-18 farad	/ lamda^2 :

       POLY		   100

       ALU1		   50

       ALU2		   25

       Cougar checks the two basic ALLIANCE rules regarding connector names:
	      If two physical connectors are connected to the same  net,  they
	      must have	the same name.
	      If  two physical connectors have the same	name, they must	be in-
	      ternally connected to the	same net.
       As a result only	one logical connector will appear in the  netlist.   A
       fatal  error  occurs  if	 one of	those two rules	is violated ( even for
       power and ground	connectors )

       When no options are specified, the current hierarchical	level  is  ex-
       tracted.	  The resulting	netlist	is the list of interconnections	of the
       current layout hierarchy	level.	Three options are available to	change
       cougar behaviour	:

       -t     Notifies a transistor level extraction, the symbolic layout cell
	      is flattened to transistor layout	before extraction.

       -f     The symbolic layout cell is flattened to the catalog  level  be-
	      fore  extraction.	  Use  "man catal" for detail on  the  catalog
	      file.  If	the catalog is empty, or doesn't exist,	the netlist is
	      an  interconection  of transistors, if  it isn't,	the netlist is
	      an interconection	of gates or blocks whose names are defined  in
	      the catalog.

       -v     Verbose  mode  on.   Each	step of	the extraction is displayed on
	      the standard  output, along  with	some statistics.

       -c     Generates	a core file representing  the  conflictuel  net,  when
	      cougar  detects  two external connectors with different names on
	      the same signal, or when it finds	two external connectors	having
	      the  same	 name but not internally connected to the same net, or
	      when it cannot correctly extract an L shaped transistor.

       -ac    Extract capacitance to ground on losig.

       -ar    Extract interconnect resistance and capacitance to ground. Value
	      of resistance foreach layer can be changed in the	RDS file.

	prompt>	cougar -v amd2901
	      Gives  a logical netlist of the chip amd2901, for	one hierarchi-
	      cal level, using verbose mode.  This would be typically used  to
	      verify  the  work	of the ring(1) router, in conjunction with lvx
	      on the specificated netlist and the extracted one.

       prompt> cat $MBK_WORK_LIB/$MBK_CATAL_NAME
       prompt> cougar -f amd2901
	      Gives a logical netlist of the chip amd2901, after a flatten op-
	      eration  stopping	 on  the  cells	specified in the catalog ( the
	      standard cell library in our case	).

       prompt> cougar -t amd2901
	      Gives a logical netlist of the amd2901 chip  at  the  transistor
	      level.   This is useful with yagle(1), to	retrieve logical equa-
	      tions from a layout.

       al(5),	  MBK_CATA_LIB(1),     MBK_WORK_LIB(1),	    MBK_CATAL_NAME(1),
       MBK_IN_PH(1), catal(5), RDS_TECHNO_NAME(1).

ASIM/LIP6			October	1, 1997			     COUGAR(1)


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