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Language(3)	      User Contributed Perl Documentation	   Language(3)

NAME
       Verilog::Language - Verilog language utilities

SYNOPSIS
	 use Verilog::Language;

	 $result = Verilog::Language::is_keyword ("wire");  # true
	 $result = Verilog::Language::is_compdirect ("`notundef");  # false
	 $result = Verilog::Language::number_value ("4'b111");	# 8
	 $result = Verilog::Language::number_bits  ("32'h1b");	# 32
	 $result = Verilog::Language::number_signed ("1'sh1");	# 1
	 @vec	 = Verilog::Language::split_bus	("[31,5:4]"); #	31, 5, 4
	 @vec	 = Verilog::Language::split_bus_nocomma	("[31:29]"); # 31, 30, 29
	 $result = Verilog::Language::strip_comments ("a/*b*/c");  # ac

DESCRIPTION
       Verilog::Language provides general utilities for	using the Verilog
       Language, such as parsing numbers or determining	what keywords exist.
       General functions will be added as needed.

FUNCTIONS
       Verilog::Language::is_keyword ($symbol_string)
	   Return true if the given symbol string is a Verilog reserved
	   keyword.  Value indicates the language standard as per the
	   `begin_keywords macro, '1364-1995', '1364-2001', '1364-2005',
	   '1800-2005',	'1800-2009', '1800-2012' or 'VAMS'.

       Verilog::Language::is_compdirect	($symbol_string)
	   Return true if the given symbol string is a Verilog compiler
	   directive.

       Verilog::Language::is_gateprim ($symbol_string)
	   Return true if the given symbol is a	built in gate primitive; for
	   example "buf", "xor", etc.

       Verilog::Language::language_keywords ($year)
	   Returns a hash for keywords for given language standard year, where
	   the value of	the hash is the	standard in which it was defined.

       Verilog::Language::language_standard ($year)
	   Sets	the language standard to indicate what are keywords.  If
	   undef, all standards	apply.	The year is indicates the language
	   standard as per the `begin_keywords macro, '1364-1995',
	   '1364-2001',	'1364-2005', '1800-2005' '1800-2009' or	'1800-2012'.

       Verilog::Language::language_maximum
	   Returns the greatest	language currently standardized, presently
	   '1800-2012'.

       Verilog::Language::number_bigint	($number_string)
	   Return the numeric value of a Verilog value stored as a
	   Math::BigInt, or undef if incorrectly formed.  You must 'use
	   Math::BigInt' yourself before calling this function.	 Note bigints
	   do not have an exact	size, so NOT of	a Math::BigInt may return a
	   different value than	verilog.  See also number_value	and
	   number_bitvector.

       Verilog::Language::number_bits ($number_string)
	   Return the number of	bits in	a value	string,	or undef if
	   incorrectly formed, _or_ not	specified.

       Verilog::Language::number_bitvector ($number_string)
	   Return the numeric value of a Verilog value stored as a
	   Bit::Vector,	or undef if incorrectly	formed.	 You must 'use
	   Bit::Vector'	yourself before	calling	this function.	The size of
	   the Vector will be that returned by number_bits.

       Verilog::Language::number_signed	($number_string)
	   Return true if the Verilog value is signed, else undef.

       Verilog::Language::number_value ($number_string)
	   Return the numeric value of a Verilog value,	or undef if
	   incorrectly formed.	It ignores any signed Verilog attributes, but
	   is is returned as a perl signed integer, so it may fail for over 31
	   bit values.	See also number_bigint and number_bitvector.

       Verilog::Language::split_bus ($bus)
	   Return a list of expanded arrays.  When passed a string like
	   "foo[5:1:2,10:9]", it will return a array with ("foo[5]", "foo[3]",
	   ...).  It correctly handles connectivity expansion also, so that
	   "x[1:0] = y[3:0]" will get intuitive	results.

       Verilog::Language::split_bus_nocomma ($bus)
	   As with split_bus, but faster.  Only	supports simple	decimal	colon
	   separated array specifications, such	as "foo[3:0]".

       Verilog::Language::strip_comments ($text)
	   Return text with any	// or /**/ comments stripped, correctly
	   handing quoted strings.  Newlines will be preserved in this
	   process.

DISTRIBUTION
       Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA
       software	tool suite.  The latest	version	is available from CPAN and
       from <http://www.veripool.org/verilog-perl>.

       Copyright 2000-2016 by Wilson Snyder.  This package is free software;
       you can redistribute it and/or modify it	under the terms	of either the
       GNU Lesser General Public License Version 3 or the Perl Artistic
       License Version 2.0.

AUTHORS
       Wilson Snyder <wsnyder@wsnyder.org>

SEE ALSO
       Verilog-Perl, Verilog::EditFiles	Verilog::Parser, Verilog::ParseSig,
       Verilog::Getopt

       And the <http://www.veripool.org/verilog-mode>Verilog-Mode package for
       Emacs.

perl v5.32.1			  2016-02-02			   Language(3)

NAME | SYNOPSIS | DESCRIPTION | FUNCTIONS | DISTRIBUTION | AUTHORS | SEE ALSO

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