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AFFECT(3)
GENPAT Package man1/alc_origin.1
ARRAY(3)
GENPAT Package man1/alc_origin.1
DECLAR(3)
GENPAT Package man1/alc_origin.1
DEF_GENPAT(3)
GENPAT Package man1/alc_origin.1
GENLIB_SET_LOCAP(3)
set the capacitance value of a logical capacitor, after its creation. man1/alc_origin.1
GENLIB_SET_LORES(3)
set the resistance value of a logical resistor, after its creation. man1/alc_origin.1
GENLIB_SET_LOSELF(3)
set the inductance value of a logical inductor, after its creation. man1/alc_origin.1
GETCPAT(3)
GENPAT Package man1/alc_origin.1
INIT(3)
GENPAT Package man1/alc_origin.1
LABEL(3)
GENPAT Package man1/alc_origin.1
MBK_FILTER_SFX(1)
define the input/output filter suffixe. man1/alc_origin.1
MBK_IN_FILTER(1)
define the input filter man1/alc_origin.1
MBK_OUT_FILTER(1)
define the input filter man1/alc_origin.1
MBK_TRACE_GETENV(1)
defines getenv() debug output man1/alc_origin.1
abl(1)
Prefixed representation for boolean functions man1/alc_origin.1
addablhexpr(3)
adds a new argument in head of an expression. man1/alc_origin.1
addablqexpr(3)
adds a new argument in queue of an expression. man1/alc_origin.1
addbddassoc(3)
creates a new association variables. man1/alc_origin.1
addbddcircuitabl(3)
converts an abl expression to a bdd node. man1/alc_origin.1
addbddcircuitin(3)
adds an input in a bdd circuit. man1/alc_origin.1
addbddcircuitout(3)
adds an output in a bdd circuit. man1/alc_origin.1
addbddnode(3)
adds a new bdd node in the bdd system. man1/alc_origin.1
addbddnodeassoc(3)
adds a bdd node in a variable association. man1/alc_origin.1
addbddnodelist(3)
adds a node in a chain_list. man1/alc_origin.1
addbddvar(3)
adds a new variable in the bdd system. man1/alc_origin.1
addbddvarafter(3)
adds a new variable, after an existing one. man1/alc_origin.1
addbddvarbefore(3)
adds a new variable, before an existing one. man1/alc_origin.1
addbddvarfirst(3)
adds a new variable, before all others. man1/alc_origin.1
addbddvarlast(3)
adds a new variable, after all others. man1/alc_origin.1
addcapa(3)
add a capacitance to a signal man1/alc_origin.1
addchain(3)
create a chain and add it to a list man1/alc_origin.1
addht(3)
create an hash table man1/alc_origin.1
addhtitem(3)
adds a new item in a hash table. man1/alc_origin.1
addlocap(3)
create a logical capacitor man1/alc_origin.1
addlocon(3)
create a logical connector man1/alc_origin.1
addlofig(3)
create a new structural cell model man1/alc_origin.1
addloins(3)
create a logical instance man1/alc_origin.1
addlomodel(3)
create a tempotary logical model and add it to a list man1/alc_origin.1
addlores(3)
create a logical resistor man1/alc_origin.1
addloself(3)
create a logical inductor man1/alc_origin.1
addlosig(3)
create a logical signal man1/alc_origin.1
addlotrs(3)
create a logical transistor man1/alc_origin.1
addnum(3)
create a num and add it to a list man1/alc_origin.1
addphcon(3)
create a physical connector man1/alc_origin.1
addphfig(3)
create a new physical cell model man1/alc_origin.1
addphins(3)
create a physical instance man1/alc_origin.1
addphref(3)
create a physical reference man1/alc_origin.1
addphseg(3)
create a physical segment man1/alc_origin.1
addphvia(3)
create a physical via man1/alc_origin.1
addptype(3)
create a ptype and add it to a ptype_list man1/alc_origin.1
addrdsfig(3)
adds a figure man1/alc_origin.1
addrdsfigrec(3)
adds a rectangle to a figure man1/alc_origin.1
addrdsins(3)
adds an instance to a figure man1/alc_origin.1
addrdsinsrec(3)
adds a rectangle to an instance man1/alc_origin.1
addrdsrecwindow(3)
adds a rectangle in the windowing of rds structure. man1/alc_origin.1
al(5)
Alliance logical format man1/alc_origin.1
alcbanner(1)
Display a standardized banner for Alliance tools man1/alc_origin.1
alliancebanner(3)
display the standardized Alliance banner man1/alc_origin.1
allocrdsfig(3)
allocs memory for a figure man1/alc_origin.1
allocrdsins(3)
allocates memory for an instance man1/alc_origin.1
allocrdsrec(3)
allocates memory for a rectangle man1/alc_origin.1
allocrdsrecwin(3)
allocates a structure used to know windows which contains a rectangle. man1/alc_origin.1
allocrdswin(3)
allocates window's table man1/alc_origin.1
allocrdswindow(3)
allocates a window structure man1/alc_origin.1
allocrdswinrec(3)
allocates a structure used to create a list of tables of rectangles. man1/alc_origin.1
ap(5)
Alliance physical format man1/alc_origin.1
append(3)
append a chain_list to an other chain_list man1/alc_origin.1
applybddnode(3)
applies an operator on two bdd nodes. man1/alc_origin.1
applybddnodeite(3)
computes the IF-THEN-ELSE logical operation. man1/alc_origin.1
applybddnodelist(3)
applies an opertor to a bdd nodes list. man1/alc_origin.1
applybddnodenot(3)
complements a bdd. man1/alc_origin.1
applybddnodeterm(3)
applies an operator on two bdd nodes. man1/alc_origin.1
asimut(1)
A simulation tool for hardware descriptions man1/alc_origin.1
aut(1)
Memory allocation, and hash tables management man1/alc_origin.1
autallocblock(3)
memory allocator man1/alc_origin.1
autallocheap(3)
heap memory allocator man1/alc_origin.1
autfreeblock(3)
releases a memory block man1/alc_origin.1
autfreeheap(3)
releases a memory block, and put it on the heap. man1/alc_origin.1
autresizeblock(3)
resizes a memory block man1/alc_origin.1
bdd(1)
Mutli Reduced Ordered Binary Decision Diagrams man1/alc_origin.1
bigvia(3)
draws a non minimal via as a bunch of vias man1/alc_origin.1
boog(1), BooG(1)
Binding and Optimizing On Gates. man1/alc_origin.1
boom(1), BOOM(1)
BOOlean Minimization man1/alc_origin.1
buildrdswindow(3)
builds windowing of a figure man1/alc_origin.1
catal(5)
catalog file format man1/alc_origin.1
checkloconorder(3)
checks the consistency of a list of logical connectors man1/alc_origin.1
clearbddsystemref(3)
clears the references for all bdd nodes. man1/alc_origin.1
clearbddsystemrefext(3)
clears the external references for all bdd nodes. man1/alc_origin.1
clearbddsystemrefint(3)
clears the internal references for all bdd nodes. man1/alc_origin.1
cofactorbddnode(3)
computes the generalized cofactor. man1/alc_origin.1
composebddnode(3)
substitutes a variable by a bdd in another bdd. man1/alc_origin.1
concatname(3)
concatenate two names with user separator man1/alc_origin.1
conmbkrds(3)
converts MBK connector to RDS rectangle man1/alc_origin.1
convertbddcircuitabl(3)
converts a bdd node to an abl expression. man1/alc_origin.1
convertbddcircuitsumabl(3)
converts a bdd node to an abl expression. man1/alc_origin.1
convertbddindexabl(3)
converts a bdd index to an abl expression. man1/alc_origin.1
convertbddmuxabl(3)
converts two bdd nodes to an abl multiplexor expression. man1/alc_origin.1
convertbddnodeabl(3)
converts a bdd node to an abl expression. man1/alc_origin.1
convertbddnodesumabl(3)
converts a bdd node to an abl expression. man1/alc_origin.1
createablatom(3)
creates an atomic expression. man1/alc_origin.1
createablbinexpr(3)
creates a binary operator expression. man1/alc_origin.1
createablnotexpr(3)
complements an expression. man1/alc_origin.1
createabloper(3)
creates the head of an operator expression. man1/alc_origin.1
createablunaryexpr(3)
creates an unary operator expression. man1/alc_origin.1
createablxorbinexpr(3)
creates an 'xor' or 'xnor' operator expression. man1/alc_origin.1
createbddcircuit(3)
creates a bdd circuit. man1/alc_origin.1
createbddsystem(3)
creates a bdd system. man1/alc_origin.1
ctl(5)
Control Temporal Logic file format. man1/alc_origin.1
decbddrefext(3)
decrements the external reference of a bdd node. man1/alc_origin.1
decbddrefint(3)
decrements the internal reference of a bdd node. man1/alc_origin.1
defab(3)
defines the abutment box of a phfig man1/alc_origin.1
delablexpr(3)
deletes an expression. man1/alc_origin.1
delablexprnum(3)
deletes an operand in an expression. man1/alc_origin.1
delbddassoc(3)
deletes a variable association. man1/alc_origin.1
delbddcircuitout(3)
deletes an output in a bdd circuit. man1/alc_origin.1
delbddnode(3)
deletes an unused bdd node. man1/alc_origin.1
delbddnodeassoc(3)
deletes a bdd node in a variable association. man1/alc_origin.1
delbddnodelist(3)
deletes a list of bdd nodes. man1/alc_origin.1
delchain(3)
delete an element of a chain_list man1/alc_origin.1
delht(3)
removes an hash table man1/alc_origin.1
delhtitem(3)
removes an item in an hash table man1/alc_origin.1
dellocap(3)
delete a logical capacitor man1/alc_origin.1
dellocon(3)
delete a logical connector man1/alc_origin.1
dellofig(3)
delete and free a logical figure man1/alc_origin.1
delloins(3)
delete a logical instance man1/alc_origin.1
dellores(3)
delete a logical resistor man1/alc_origin.1
delloself(3)
delete a logical inductor man1/alc_origin.1
dellosig(3)
delete a logical signal man1/alc_origin.1
dellotrs(3)
delete a logical transistor man1/alc_origin.1
delnum(3)
delete an element of a num_list man1/alc_origin.1
delphcon(3)
delete a physical connector man1/alc_origin.1
delphfig(3)
delete and free a physical figure man1/alc_origin.1
delphins(3)
delete a physical instance man1/alc_origin.1
delphref(3)
delete a physical reference man1/alc_origin.1
delphseg(3)
delete a physical segment man1/alc_origin.1
delphvia(3)
delete a physical via man1/alc_origin.1
delptype(3)
delete an element of a ptype_list man1/alc_origin.1
delrdsfig(3)
deletes a figure man1/alc_origin.1
delrdsfigrec(3)
deletes a rectangle of a figure man1/alc_origin.1
delrdsins(3)
deletes an instance of a figure man1/alc_origin.1
delrdsinsrec(3)
deletes a rectangle of an instance man1/alc_origin.1
delrdsrecwindow(3)
deletes a rectangle from the windowing of rds structure. man1/alc_origin.1
destroybddassoc(3)
frees all the variable associations. man1/alc_origin.1
destroybddcircuit(3)
destroys a bdd circuit. man1/alc_origin.1
destroybddsystem(3)
destroys a bdd system. man1/alc_origin.1
destroyrdswindow(3)
destroys windowing of a figure man1/alc_origin.1
devablxorexpr(3)
develops 'xor', 'nxor' in an expression. man1/alc_origin.1
devdupablxorexpr(3)
duplicates and develops 'xor', 'nxor'. man1/alc_origin.1
downstr(3)
convert a string to lower case man1/alc_origin.1
dupablexpr(3)
duplicates an expression. man1/alc_origin.1
existbddnodeassocoff(3)
computes an existantial quantification. man1/alc_origin.1
existbddnodeassocon(3)
computes an existantial quantification. man1/alc_origin.1
figmbkrds(3)
converts MBK figure to RDS figure man1/alc_origin.1
filepath(3)
return the whole search path of a file man1/alc_origin.1
flatablexpr(3)
merges the operators of an expression man1/alc_origin.1
flatlo(1)
FLATen LOgical figure man1/alc_origin.1
flatph(1)
FLATen PHysical figure man1/alc_origin.1
flattenlofig(3)
flatten a instance in a logical figure man1/alc_origin.1
flattenphfig(3), flatenphfig(3)
flatten a instance in a figure man1/alc_origin.1
fmi(1)
FSM state miminization man1/alc_origin.1
freeablexpr(3)
frees an expression. man1/alc_origin.1
freechain(3)
free a chain_list man1/alc_origin.1
freelomodel(3)
free a lofig_list for temporary models man1/alc_origin.1
freenum(3)
free a num_list man1/alc_origin.1
freeptype(3)
free a ptype_list man1/alc_origin.1
freerdsfig(3)
frees memory associated to a figure man1/alc_origin.1
freerdsins(3)
frees memory associated to an instance man1/alc_origin.1
freerdsrec(3)
free memory associated to a rectangle man1/alc_origin.1
fsm(1)
Finite State Machine representation. man1/alc_origin.1
fsm(5)
Alliance VHDL Finite State Machine description subset. man1/alc_origin.1
fsp(1)
Formal proof between two FSM descriptions man1/alc_origin.1
garbagebddsystem(3)
Forces a bdd garbage collection. man1/alc_origin.1
getablexprdepth(3)
gives the depth of an expression. man1/alc_origin.1
getablexprlength(3)
gives the length of an expression. man1/alc_origin.1
getablexprmax(3)
applies a function to all operands. man1/alc_origin.1
getablexprmin(3)
applies a function to all operands. man1/alc_origin.1
getablexprnum(3)
gives a specified operand of an expression. man1/alc_origin.1
getablexprnumatom(3)
gives the number of atom in an expression. man1/alc_origin.1
getablexprnumbinoper(3)
gives the number of binary operators in an expression. man1/alc_origin.1
getablexprnumocc(3)
how many times a name appears in an expression. man1/alc_origin.1
getablexprsupport(3)
gives the expression's support. man1/alc_origin.1
getbddnodenum(3)
gets the number of nodes in a bdd. man1/alc_origin.1
getbddnodesize(3)
gets the number of nodes in a bdd. man1/alc_origin.1
getbddnodesupport(3)
gives the variable support of a bdd node. man1/alc_origin.1
getbddvarbyindex(3)
converts bdd index to a variable number. man1/alc_origin.1
getbddvarindex(3)
converts a variable number in a bdd index. man1/alc_origin.1
getbddvarnode(3)
gives the bdd node of a variable. man1/alc_origin.1
gethtitem(3)
searches an item in a hash table man1/alc_origin.1
getlocap(3)
retrieve a logical capacitor man1/alc_origin.1
getlocon(3)
retrieve a logical connector man1/alc_origin.1
getlofig(3)
give back a pointer to a lofig man1/alc_origin.1
getloins(3)
retrieve a logical instance man1/alc_origin.1
getlomodel(3)
retrieve a model from a lofig_list man1/alc_origin.1
getlores(3)
retrieve a logical resistor man1/alc_origin.1
getloself(3)
retrieve a logical inductor man1/alc_origin.1
getlosig(3)
retrieve a logical signal man1/alc_origin.1
getphcon(3)
retrieve a physical connector man1/alc_origin.1
getphfig(3)
give back a pointer to a phfig man1/alc_origin.1
getphins(3)
retrieve a physical instance man1/alc_origin.1
getphref(3)
retrieve a physical reference man1/alc_origin.1
getptype(3)
retrieve a ptype from a ptype_list man1/alc_origin.1
getrdsmodellist(3)
gets model list of the instances of a figure man1/alc_origin.1
getsigname(3)
choose a signal name in alias list man1/alc_origin.1
givelosig(3)
give a logical signal man1/alc_origin.1
guessextdir(3)
guess external connectors directions from internal connectors directions man1/alc_origin.1
implybddnode(3)
computes a bdd that implies a conjonction of two bdd nodes. man1/alc_origin.1
incatalog(3)
test if cell belongs to the catalog file man1/alc_origin.1
incatalogdelete(3)
test if cell belongs to the catalog file man1/alc_origin.1
incatalogfeed(3)
test if cell belongs to the catalog file man1/alc_origin.1
incataloggds(3)
test if cell belongs to the catalog file man1/alc_origin.1
incbddrefext(3)
increments the external reference of a bdd node. man1/alc_origin.1
incbddrefint(3)
increments the internal reference of a bdd node. man1/alc_origin.1
insconmbkrds(3)
adds in RDS instance all the connectors of MBK instance man1/alc_origin.1
insmbkrds(3)
converts MBK figure to RDS figure man1/alc_origin.1
insrefmbkrds(3)
adds in RDS instance all the references of MBK instance. man1/alc_origin.1
inssegmbkrds(3)
adds in RDS instance all the segments of MBK instance man1/alc_origin.1
instanceface(3)
returns the face of a connector in a placed instance man1/alc_origin.1
instr(3)
find an occurence of a string in a string, starting at a specified character. man1/alc_origin.1
insviambkrds(3)
adds to RDS instance all the contacts from MBK instance man1/alc_origin.1
intersectbddnode(3)
tests for an intersection between two bdd nodes. man1/alc_origin.1
isablbinaryoper(3)
tests if an operator is binary. man1/alc_origin.1
isablequalexpr(3)
tests if two expressions are strictly identicals. man1/alc_origin.1
isabloperinexpr(3)
tests if an operator appears in an expression. man1/alc_origin.1
isablsimilarexpr(3)
tests if two expressions have the same morphology. man1/alc_origin.1
isablunaryoper(3)
tests if an operator is unary. man1/alc_origin.1
isbddvarinsupport(3)
tests if a variable appears in a bdd. man1/alc_origin.1
isck(3)
-tells if a name is the pattern defined by the user man1/alc_origin.1
isvdd(3)
-tells if a name contains the pattern defined by the user man1/alc_origin.1
isvss(3)
-tells if a name contains the pattern defined by the user man1/alc_origin.1
k2f(1)
FSM translator ALLIANCE format from/to Berkeley format man1/alc_origin.1
l2p(1)
Creates a PostScript file from a symbolic layout file,or from a physical layout file. man1/alc_origin.1
lax(5)
Parameter file for logic synthesis man1/alc_origin.1
loadlofig(3)
load a new logical cell model from disk man1/alc_origin.1
loadphfig(3)
load a new physical cell model from disk man1/alc_origin.1
loadrdsfig(3)
give back a pointer to a figure man1/alc_origin.1
loadrdsparam(3)
load parameters from symbolic to real conversion. man1/alc_origin.1
lofigchain(3)
creates a netlist in terms of connectors on signals man1/alc_origin.1
log(1)
logical representations for boolean functions and utilities. man1/alc_origin.1
loon(1), LooN(1)
Local optimizations of Nets. man1/alc_origin.1
mapablanyexpr(3)
applies a function to all operands. man1/alc_origin.1
mapableveryexpr(3)
applies a function to all operands. man1/alc_origin.1
mapablexpr(3)
applies a function to all operands. man1/alc_origin.1
mapabloperexpr(3)
applies a function to all operands. man1/alc_origin.1
markbddnode(3)
marks bdd node with a specified mask. man1/alc_origin.1
mbk(3)
Generic layout ,netlist and utility data structures man1/alc_origin.1
mbkalloc(3)
mbk memory allocator man1/alc_origin.1
mbkenv(3)
set user preferences man1/alc_origin.1
mbkfopen(3)
open a file with several search pathes man1/alc_origin.1
mbkfree(3)
mbk memory allocator man1/alc_origin.1
mbkgetenv(3)
get an environment variable man1/alc_origin.1
mbkps(3)
mbk process state man1/alc_origin.1
mbkrealloc(3)
mbk memory reallocator man1/alc_origin.1
mbksetautoackchld(3)
Tells Alliance to automatically handle terminaison of child process. man1/alc_origin.1
mbkunlink(3)
delete a file in the WORK_LIBP. man1/alc_origin.1
mbkwaitpid(3)
wait for the end of a particular child process. man1/alc_origin.1
mlodebug(3)
logical data structure contents debug function man1/alc_origin.1
modelmbkrds(3)
gets all models of instances contained in a figure. man1/alc_origin.1
moka(1), MOKA(1)
Model checker ancestor man1/alc_origin.1
mphdebug(3)
physical data structure contents debug function man1/alc_origin.1
namealloc(3)
hash table for strings man1/alc_origin.1
namefind(3)
hash table for strings man1/alc_origin.1
nameindex(3)
concatenate a name and index with user separator man1/alc_origin.1
naturalstrcmp(3)
compare string in alphabetical order for letters and numerical for digits. man1/alc_origin.1
ocp(1)
Standard Cell Placer man1/alc_origin.1
pat2spi(1)
PAT ALLIANCE format translator to Spice PWL format man1/alc_origin.1
polarablexpr(3)
moves inverters to the atomic level. man1/alc_origin.1
polardupablexpr(3)
duplicates an expression and moves down the inverters. man1/alc_origin.1
prol(5)
define the rules for symbolic to real layout translation man1/alc_origin.1
proof(1)
Formal proof between two behavioural descriptions man1/alc_origin.1
rdsalloc(3)
memory allocation function man1/alc_origin.1
rdsenv(3)
set user preference man1/alc_origin.1
rdsfree(3)
free memory place man1/alc_origin.1
refmbkrds(3)
adds to RDS figure a references from a MBK figure man1/alc_origin.1
relprodbddnodeassoc(3)
computes a relational product. man1/alc_origin.1
reorderbddsystemdynamic(3)
specifies the dynamic bdd reorder parameters. man1/alc_origin.1
reorderbddsystemsimple(3)
reorders the bdd nodes of a bdd system. man1/alc_origin.1
reorderbddsystemtop(3)
reorders the bdd nodes of a bdd system. man1/alc_origin.1
reorderbddsystemwindow(3)
reorders the bdd nodes of a bdd system. man1/alc_origin.1
resetbddcircuit(3)
resets a bdd circuit. man1/alc_origin.1
resetbddsystem(3)
resets a bdd system. man1/alc_origin.1
restorealldir(3)
restore all instances' connectors directions man1/alc_origin.1
restoredirvbe(3)
restore connectors directions from behavioral view man1/alc_origin.1
restrictbddnode(3)
substitutes a variable by a zero or one, in a bdd. man1/alc_origin.1
reverse(3)
reverse a list of chained elements man1/alc_origin.1
rflattenlofig(3)
recursivly flatten a figure man1/alc_origin.1
rflattenphfig(3)
recursivly flatten a figure man1/alc_origin.1
roundrdsrec(3)
adjusts a rectangle to lambda grid step man1/alc_origin.1
satisfybddnode(3)
finds a satisfying path for a bdd node. man1/alc_origin.1
savelofig(3)
save a logical figure on disk man1/alc_origin.1
savephfig(3)
save a physical figure on disk man1/alc_origin.1
saverdsfig(3)
save a physical figure on disk. man1/alc_origin.1
scapin(1)
Scan path insertion man1/alc_origin.1
searchbddcircuitin(3)
searchs an input in a bdd circuit. man1/alc_origin.1
searchbddcircuitout(3)
searchs an output in a bdd circuit. man1/alc_origin.1
searchrdsfig(3)
searchs by name a figure in the list of figures man1/alc_origin.1
segmbkrds(3)
adds to RDS figure a segment from a MBK figure man1/alc_origin.1
setbddrefext(3)
increments the external reference, and decrements the internal reference of a bdd node. man1/alc_origin.1
sethtitem(3)
test and set an item in an hash table. man1/alc_origin.1
setlocap(3)
set the capacitance value of a logical capacitor man1/alc_origin.1
setlores(3)
set the resistance value of a logical resistor man1/alc_origin.1
setloself(3)
set the inductance value of a logical inductor man1/alc_origin.1
simpablexpr(3)
simplies an expression. man1/alc_origin.1
simpbddnodedcoff(3)
simplifies a bdd with don't cares on its off-set part. man1/alc_origin.1
simpbddnodedcon(3)
simplifies a bdd with don't cares on its on-set part. man1/alc_origin.1
simpdupablexpr(3)
duplicates and simplies an expression. man1/alc_origin.1
sortlocon(3)
sort the logical connectors of a figure by name man1/alc_origin.1
sortlosig(3)
sort the logical signals of a figure by name man1/alc_origin.1
spi(5)
Alliance parser and driver for Spice netlist. man1/alc_origin.1
substablexpr(3)
substitutes a given atom by an expression. man1/alc_origin.1
substbddnodeassoc(3)
substitutes a set of variables with a set of bdd node. man1/alc_origin.1
substdupablexpr(3)
substitutes a given atom by an expression. man1/alc_origin.1
swapbddvar(3)
swaps two contiguous variables. man1/alc_origin.1
sxlib(5)
a portable CMOS Standard Cell Library man1/alc_origin.1
syf(1), SYF(1)
Finite State Machine synthesizer. man1/alc_origin.1
testbddcircuit(3)
debugs a bdd circuit. man1/alc_origin.1
unflatablexpr(3)
unflats the operators of an expression man1/alc_origin.1
unflattenlofig(3)
creates a hierarchy level from instances of a figure man1/alc_origin.1
unmarkbddnode(3)
unmarks bdd node with a specified mask. man1/alc_origin.1
unsetbddrefext(3)
increments the internal reference, and decrements the external reference of a bdd node. man1/alc_origin.1
upstr(3)
convert a string to upper case man1/alc_origin.1
vasy(1), VASY(1)
VHDL Analyzer for Synthesis man1/alc_origin.1
vasy(5)
VHDL RTL subset. man1/alc_origin.1
vbe(5)
VHDL behavioural subset. man1/alc_origin.1
vhdl(5), ALLIANCE(5)
VHDL Subset man1/alc_origin.1
vhdlablname(3)
returns a compatible VHDL name. man1/alc_origin.1
vhdlablvector(3)
gives the index and the name of a vectorized name. man1/alc_origin.1
viambkrds(3)
adds to RDS figure a contact from a MBK figure man1/alc_origin.1
viewablexpr(3)
displays an expression. man1/alc_origin.1
viewablexprfile(3)
displays an expression in a file. man1/alc_origin.1
viewablexprstr(3)
displays an expression in a str. man1/alc_origin.1
viewbddcircuit(3)
displays a bdd circuit. man1/alc_origin.1
viewbddnode(3)
displays a bdd node. man1/alc_origin.1
viewbddsystem(3)
displays a bdd system. man1/alc_origin.1
viewbddsysteminfo(3)
displays statistical informations. man1/alc_origin.1
viewht(3)
displays a hash table contents man1/alc_origin.1
viewlo(3)
scan all lofig_lists and display their elements man1/alc_origin.1
viewlocap(3)
display elements of a locap_list man1/alc_origin.1
viewlofig(3)
display elements of a lofig_list man1/alc_origin.1
viewloins(3)
display elements of a loins_list man1/alc_origin.1
viewloinscon(3)
display elements of a locon_list attached to an instance man1/alc_origin.1
viewlores(3)
display elements of a lores_list man1/alc_origin.1
viewloself(3)
display elements of a loself_list man1/alc_origin.1
viewlosig(3)
display elements of a losig_list man1/alc_origin.1
viewlotrs(3)
display elements of a lotrs_list man1/alc_origin.1
viewph(3)
display all the phfig_lists and their elements man1/alc_origin.1
viewphcon(3)
display elements of a phcon_list man1/alc_origin.1
viewphins(3)
display elements of a phins_list man1/alc_origin.1
viewphref(3)
display elements of a phref_list man1/alc_origin.1
viewphseg(3)
display elements of a phseg_list man1/alc_origin.1
viewrdsfig(3)
view caracteristics of a figure man1/alc_origin.1
viewrdsins(3)
Displays caracteristics of an instance man1/alc_origin.1
viewrdsparam(3)
displays tables in memory filled by loadrdsparam function. man1/alc_origin.1
viewrdsrec(3)
Displays caracteristics of a rectangle man1/alc_origin.1
viewrdswindow(3)
displays caracteristics of the windowing. man1/alc_origin.1
viewrfmcon(3)
displays connector caracteristics in MBK and RDS format. man1/alc_origin.1
viewrfmfig(3)
displays figure caracteristics in MBK and RDS format. man1/alc_origin.1
viewrfmins(3)
displays instance caracteristics in MBK and RDS format. man1/alc_origin.1
viewrfmrec(3)
displays rectangle caracteristics in RDS format. man1/alc_origin.1
viewrfmref(3)
displays reference caracteristics in MBK and RDS format. man1/alc_origin.1
viewrfmseg(3)
displays segment caracteristics in MBK and RDS format. man1/alc_origin.1
viewrfmvia(3)
displays contact caracteristics in MBK and RDS format. man1/alc_origin.1
vst(5)
VHDL structural subset. man1/alc_origin.1
x2y(1)
Netlist Format converter man1/alc_origin.1
xyflat(3)
compute hierarchical coordinates man1/alc_origin.1
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