Skip site navigation (1)Skip section navigation (2)

FreeBSD Man Pages

Man Page or Keyword Search:
Man Architecture
Apropos Keyword Search (all sections) Output format
home | help
PMC.CORE2(3)	       FreeBSD Library Functions Manual		  PMC.CORE2(3)

NAME
     pmc.core2 -- measurement events for Intel Core2 family CPUs

LIBRARY
     Performance Monitoring Counters Interface Library (libpmc,	-lpmc)

SYNOPSIS
     #include <pmc.h>

DESCRIPTION
     Intel Core2 CPUs contain PMCs conforming to version 2 of the Intel	per-
     formance measurement architecture.	 These CPUs may	contain	up to two
     classes of	PMCs:

     PMC_CLASS_IAF     Fixed-function counters that count only one hardware
		       event per counter.

     PMC_CLASS_IAP     Programmable counters that may be configured to count
		       one of a	defined	set of hardware	events.

     The number	of PMCs	available in each class	and their widths need to be
     determined	at run time by calling pmc_cpuinfo(3).

     Intel Core2 PMCs are documented in	"Volume	3: System Programming Guide",
     IA-32 Intel(R) Architecture Software Developer's Manual, Order Number
     253669-027US, Intel Corporation, July 2008.

   CORE2 FIXED FUNCTION	PMCS
     These PMCs	and their supported events are documented in pmc.iaf(3).  Not
     all CPUs in this family implement fixed-function counters.

   CORE2 PROGRAMMABLE PMCS
     The programmable PMCs support the following capabilities:

     Capability		  Support
     PMC_CAP_CASCADE	  No
     PMC_CAP_EDGE	  Yes
     PMC_CAP_INTERRUPT	  Yes
     PMC_CAP_INVERT	  Yes
     PMC_CAP_READ	  Yes
     PMC_CAP_PRECISE	  No
     PMC_CAP_SYSTEM	  Yes
     PMC_CAP_TAGGING	  No
     PMC_CAP_THRESHOLD	  Yes
     PMC_CAP_USER	  Yes
     PMC_CAP_WRITE	  Yes

   Event Qualifiers
     Event specifiers for these	PMCs support the following common qualifiers:

     cmask=value
	     Configure the PMC to increment only if the	number of configured
	     events measured in	a cycle	is greater than	or equal to value.

     edge    Configure the PMC to count	the number of de-asserted to asserted
	     transitions of the	conditions expressed by	the other qualifiers.
	     If	specified, the counter will increment only once	whenever a
	     condition becomes true, irrespective of the number	of clocks dur-
	     ing which the condition remains true.

     inv     Invert the	sense of comparison when the ``cmask'' qualifier is
	     present, making the counter increment when	the number of events
	     per cycle is less than the	value specified	by the ``cmask'' qual-
	     ifier.

     os	     Configure the PMC to count	events happening at processor privi-
	     lege level	0.

     usr     Configure the PMC to count	events occurring at privilege levels
	     1,	2 or 3.

     If	neither	of the ``os'' or ``usr'' qualifiers are	specified, the default
     is	to enable both.

     Events that require core-specificity to be	specified use a	additional
     qualifier ``core=core'', where argument core is one of:

     all     Measure event conditions on all cores.

     this    Measure event conditions on this core.

     The default is ``this''.

     Events that require an agent qualifier to be specified use	an additional
     qualifier ``agent=agent'',	where argument agent is	one of:

     this    Measure events associated with this bus agent.

     any     Measure events caused by any bus agent.

     The default is ``this''.

     Events that require a hardware prefetch qualifier to be specified use an
     additional	qualifier ``prefetch=prefetch'', where argument	prefetch is
     one of:

     both     Include all prefetches.

     only     Only count hardware prefetches.

     exclude  Exclude hardware prefetches.

     The default is ``both''.

     Events that require a cache coherence qualifier to	be specified use an
     additional	qualifier ``cachestate=state'',	where argument state contains
     one or more of the	following letters:

     e	     Count cache lines in the exclusive	state.

     i	     Count cache lines in the invalid state.

     m	     Count cache lines in the modified state.

     s	     Count cache lines in the shared state.

     The default is ``eims''.

     Events that require a snoop response qualifier to be specified use	an
     additional	qualifier ``snoopresponse=response'', where argument response
     comprises of the following	keywords separated by ``+'' signs:

     clean   Measure CLEAN responses.

     hit     Measure HIT responses.

     hitm    Measure HITM responses.

     The default is to measure all the above responses.

     Events that require a snoop type qualifier	use an additional qualifier
     ``snooptype=type'', where argument	type comprises the one of the follow-
     ing keywords:

     cmp2i   Measure CMP2I snoops.

     cmp2s   Measure CMP2S snoops.

     The default is to measure both snoops.

   Event Specifiers (Programmable PMCs)
     Core2 programmable	PMCs support the following events:

     BACLEARS
	     (Event E6H, Umask 00H) The	number of times	the front end is
	     resteered.

     BOGUS_BR
	     (Event E4H, Umask 00H) The	number of byte sequences mistakenly
	     detected as taken branch instructions.

     BR_BAC_MISSP_EXEC
	     (Event 8AH, Umask 00H) The	number of branch instructions that
	     were mispredicted when decoded.

     BR_CALL_MISSP_EXEC
	     (Event 93H, Umask 00H) The	number of mispredicted CALL instruc-
	     tions that	were executed.

     BR_CALL_EXEC
	     (Event 92H, Umask 00H) The	number of CALL instructions executed.

     BR_CND_EXEC
	     (Event 8BH, Umask 00H) The	number of conditional branches exe-
	     cuted, but	not necessarily	retired.

     BR_CND_MISSP_EXEC
	     (Event 8CH, Umask 00H) The	number of mispredicted conditional
	     branches executed.

     BR_IND_CALL_EXEC
	     (Event 94H, Umask 00H) The	number of indirect CALL	instructions
	     executed.

     BR_IND_EXEC
	     (Event 8DH, Umask 00H) The	number of indirect branch instructions
	     executed.

     BR_IND_MISSP_EXEC
	     (Event 8EH, Umask 00H) The	number of mispredicted indirect	branch
	     instructions executed.

     BR_INST_DECODED
	     (Event E0H, Umask 00H) The	number of branch instructions decoded.

     BR_INST_EXEC
	     (Event 88H, Umask 00H) The	number of branches executed, but not
	     necessarily retired.

     BR_INST_RETIRED.ANY
	     (Event C4H, Umask 00H) (Alias "Branch Instruction Retired") The
	     number of branch instructions retired.  This is an	architectural
	     performance event.

     BR_INST_RETIRED.MISPRED
	     (Event C5H, Umask 00H) (Alias "Branch Misses Retired") The	number
	     of	mispredicted branch instructions retired.  This	is an archi-
	     tectural performance event.

     BR_INST_RETIRED.MISPRED_NOT_TAKEN
	     (Event C4H, Umask 02H) The	number of not taken branch instruc-
	     tions retired that	were mispredicted.

     BR_INST_RETIRED.MISPRED_TAKEN
	     (Event C4H, Umask 08H) The	number taken branch instructions
	     retired that were mispredicted.

     BR_INST_RETIRED.PRED_NOT_TAKEN
	     (Event C4H, Umask 01H) The	number of not taken branch instruc-
	     tions retired that	were correctly predicted.

     BR_INST_RETIRED.PRED_TAKEN
	     (Event C4H, Umask 04H) The	number of taken	branch instructions
	     retired that were correctly predicted.

     BR_INST_RETIRED.TAKEN
	     (Event C4H, Umask 0CH) The	number of taken	branch instructions
	     retired.

     BR_MISSP_EXEC
	     (Event 89H, Umask 00H) The	number of mispredicted branch instruc-
	     tions that	were executed.

     BR_RET_MISSP_EXEC
	     (Event 90H, Umask 00H) The	number of mispredicted RET instruc-
	     tions executed.

     BR_RET_BAC_MISSP_EXEC
	     (Event 91H, Umask 00H) The	number of RET instructions executed
	     that were mispredicted at decode time.

     BR_RET_EXEC
	     (Event 8FH, Umask 00H) The	number of RET instructions executed.

     BR_TKN_BUBBLE_1
	     (Event 97H, Umask 00H) The	number of branch predicted taken with
	     bubble 1.

     BR_TKN_BUBBLE_2
	     (Event 98H, Umask 00H) The	number of branch predicted taken with
	     bubble 2.

     BUSQ_EMPTY	[,core=core]
	     (Event 7DH) The number of cycles during which the core did	not
	     have any pending transactions in the bus queue.

     BUS_BNR_DRV [,agent=agent]
	     (Event 61H) The number of Bus Not Ready signals asserted on the
	     bus.

     BUS_DATA_RCV [,core=core]
	     (Event 64H) The number of bus cycles during which the processor
	     is	receiving data.

     BUS_DRDY_CLOCKS [,agent=agent]
	     (Event 62H) The number of bus cycles during which the Data	Ready
	     signal is asserted	on the bus.

     BUS_HIT_DRV [,agent=agent]
	     (Event 7AH) The number of bus cycles during which the processor
	     drives the	HIT# pin.

     BUS_HITM_DRV [,agent=agent]
	     (Event 7BH) The number of bus cycles during which the processor
	     drives the	HITM# pin.

     BUS_IO_WAIT [,core=core]
	     (Event 7FH) The number of core cycles during which	I/O requests
	     wait in the bus queue.

     BUS_LOCK_CLOCKS [,agent=agent] [,core=core]
	     (Event 63H) The number of bus cycles during which the LOCK	signal
	     was asserted on the bus.

     BUS_REQUEST_OUTSTANDING [,agent=agent] [,core=core]
	     (Event 60H) The number of pending full cache line read transac-
	     tions on the bus occurring	in each	cycle.

     BUS_TRANS_P [,agent=agent]	[,core=core]
	     (Event 6BH) The number of partial bus transactions.

     BUS_TRANS_IFETCH [,agent=agent] [,core=core]
	     (Event 68H) The number of instruction fetch full cache line bus
	     transactions.

     BUS_TRANS_INVAL [,agent=agent] [,core=core]
	     (Event 69H) The number of invalidate bus transactions.

     BUS_TRANS_PWR [,agent=agent] [,core=core]
	     (Event 6AH) The number of partial write bus transactions.

     BUS_TRANS_DEF [,agent=agent] [,core=core]
	     (Event 6DH) The number of deferred	bus transactions.

     BUS_TRANS_BURST [,agent=agent] [,core=core]
	     (Event 6EH) The number of burst transactions.

     BUS_TRANS_MEM [,agent=agent] [,core=core]
	     (Event 6FH) The number of memory bus transactions.

     BUS_TRANS_ANY [,agent=agent] [,core=core]
	     (Event 70H) The number of bus transactions	of any kind.

     BUS_TRANS_BRD [,agent=agent] [,core=core]
	     (Event 65H) The number of burst read transactions.

     BUS_TRANS_IO [,agent=agent] [,core=core]
	     (Event 6CH) The number of completed I/O bus transactions due to
	     IN	and OUT	instructions.

     BUS_TRANS_RFO [,agent=agent] [,core=core]
	     (Event 66H) The number of Read For	Ownership bus transactions.

     BUS_TRANS_WB [,agent=agent] [,core=core]
	     (Event 67H) The number explicit write-back	bus transactions due
	     to	dirty line evictions.

     CMP_SNOOP [,core=core] [,snooptype=snoop]
	     (Event 78H) The number of times the L1 data cache is snooped by
	     the other core in the same	processor.

     CPU_CLK_UNHALTED.BUS
	     (Event 3CH, Umask 01H) (Alias "Unhalted Reference Cycles")	The
	     number of bus cycles when the core	is not in the halt state.
	     This is an	architectural performance event.

     CPU_CLK_UNHALTED.CORE_P
	     (Event 3CH, Umask 00H) (Alias "Unhalted Core Cycles") The number
	     of	core cycles while the core is not in a halt state.  This is an
	     architectural performance event.

     CPU_CLK_UNHALTED.NO_OTHER
	     (Event 3CH, Umask 02H) The	number of bus cycles during which the
	     core remains unhalted and the other core is halted.

     CYCLES_DIV_BUSY
	     (Event 14H, Umask 00H) The	number of cycles the divider is	busy.
	     This event	is only	available on PMC0.

     CYCLES_INT_MASKED
	     (Event C6H, Umask 01H) The	number of cycles during	which inter-
	     rupts are disabled.

     CYCLES_INT_PENDING_AND_MASKED
	     (Event C6H, Umask 02H) The	number of cycles during	which there
	     were pending interrupts while interrupts were disabled.

     CYCLES_L1I_MEM_STALLED
	     (Event 86H, Umask 00H) The	number of cycles for which an instruc-
	     tion fetch	stalls.

     DELAYED_BYPASS.FP
	     (Event 19H, Umask 00H) The	number of floating point operations
	     that used data immediately	after the data was generated by	a non
	     floating point execution unit.

     DELAYED_BYPASS.LOAD
	     (Event 19H, Umask 01H) The	number of delayed bypass penalty
	     cycles that a load	operation incurred.

     DELAYED_BYPASS.SIMD
	     (Event 19H, Umask 02H) The	number of times	SIMD operations	use
	     data immediately after data, was generated	by a non-SIMD execu-
	     tion unit.

     DIV     (Event 13H, Umask 00H) The	number of divide operations executed.
	     This event	is only	available on PMC1.

     DTLB_MISSES.ANY
	     (Event 08H, Umask 01H) The	number of Data TLB misses, including
	     misses that result	from speculative accesses.

     DTLB_MISSES.L0_MISS_LD
	     (Event 08H, Umask 04H) The	number of level	0 DTLB misses due to
	     load operations.

     DTLB_MISSES.MISS_LD
	     (Event 08H, Umask 02H) The	number of Data TLB misses due to load
	     operations.

     DTLB_MISSES.MISS_ST
	     (Event 08H, Umask 08H) The	number of Data TLB misses due to store
	     operations.

     EIST_TRANS
	     (Event 3AH, Umask 00H) The	number of Enhanced Intel SpeedStep
	     Technology	transitions.

     ESP.ADDITIONS
	     (Event ABH, Umask 02H) The	number of automatic additions to the
	     %esp register.

     ESP.SYNCH
	     (Event ABH, Umask 01H) The	number of times	the %esp register was
	     explicitly	used in	an address expression after it is implicitly
	     used by a PUSH or POP instruction.

     EXT_SNOOP [,agent=agent] [,snoopresponse=response]
	     (Event 77H) The number of snoop responses to bus transactions.

     FP_ASSIST
	     (Event 11H, Umask 00H) The	number of floating point operations
	     executed that needed a microcode assist.

     FP_COMP_OPS_EXE
	     (Event 10H, Umask 00H) The	number of floating point computational
	     micro-ops executed.  The event is available only on PMC0.

     FP_MMX_TRANS_TO_FP
	     (Event CCH, Umask 02H) The	number of transitions from MMX
	     instructions to floating point instructions.

     FP_MMX_TRANS_TO_MMX
	     (Event CCH, Umask 01H) The	number of transitions from floating
	     point instructions	to MMX instructions.

     HW_INT_RCV
	     (Event C8H, Umask 00H) The	number of hardware interrupts
	     received.

     IDLE_DURING_DIV
	     (Event 18H, Umask 00H) The	number of cycles the divider is	busy
	     and no other execution unit or load operation was in progress.
	     This event	is available only on PMC0.

     ILD_STALL
	     (Event 87H, Umask 00H) The	number of cycles the instruction
	     length decoder stalled due	to a length changing prefix.

     INST_QUEUE.FULL
	     (Event 83H, Umask 02H) The	number of cycles during	which the
	     instruction queue is full.

     INST_RETIRED.ANY_P
	     (Event C0H, Umask 00H) (Alias "Instruction	Retired") The number
	     of	instructions retired.  This is an architectural	performance
	     event.

     INST_RETIRED.LOADS
	     (Event C0H, Umask 01H) The	number of instructions retired that
	     contained a load operation.

     INST_RETIRED.OTHER
	     (Event C0H, Umask 04H) The	number of instructions retired that
	     did not contain a load or a store operation.

     INST_RETIRED.STORES
	     (Event C0H, Umask 02H) The	number of instructions retired that
	     contained a store operation.

     INST_RETIRED.VM_H
	     (Event C0H, Umask 08H) (Core2Extreme) The number of instructions
	     retired while in VMX root operation.

     ITLB.FLUSH
	     (Event 82H, Umask 40H) The	number of ITLB flushes.

     ITLB.LARGE_MISS
	     (Event 82H, Umask 10H) The	number of instruction fetches from
	     large pages that miss the ITLB.

     ITLB.MISSES
	     (Event 82H, Umask 12H) The	number of instruction fetches from
	     both large	and small pages	that miss the ITLB.

     ITLB.SMALL_MISS
	     (Event 82H, Umask 02H) The	number of instruction fetches from
	     small pages that miss the ITLB.

     ITLB_MISS_RETIRED
	     (Event C9H, Umask 00H) The	number of retired instructions that
	     missed the	ITLB when they were fetched.

     L1D_ALL_REF
	     (Event 43H, Umask 01H) The	number of references to	L1 data	cache
	     counting loads and	stores of to all memory	types.

     L1D_ALL_CACHE_REF
	     (Event 43H, Umask 02H) The	number of data reads and writes	to
	     cacheable memory.

     L1D_CACHE_LOCK [,cachestate=state]
	     (Event 42H) The number of locked reads from cacheable memory.

     L1D_CACHE_LOCK_DURATION
	     (Event 42H, Umask 10H) The	number of cycles during	which any
	     cache line	is locked by any locking instruction.

     L1D_CACHE_LD [,cachestate=state]
	     (Event 40H) The number of data reads from cacheable memory
	     excluding locked reads.

     L1D_CACHE_ST [,cachestate=state]
	     (Event 41H) The number of data writes to cacheable	memory exclud-
	     ing locked	writes.

     L1D_M_EVICT
	     (Event 47H, Umask 00H) The	number of modified cache lines evicted
	     from L1 data cache.

     L1D_M_REPL
	     (Event 46H, Umask 00H) The	number of modified lines allocated in
	     L1	data cache.

     L1D_PEND_MISS
	     (Event 48H, Umask 00H) The	total number of	outstanding L1 data
	     cache misses at any clock.

     L1D_PREFETCH.REQUESTS
	     (Event 4EH, Umask 10H) The	number of times	L1 data	cache
	     requested to prefetch a data cache	line.

     L1D_REPL
	     (Event 45H, Umask 0FH) The	number of lines	brought	into L1	data
	     cache.

     L1D_SPLIT.LOADS
	     (Event 49H, Umask 01H) The	number of load operations that span
	     two cache lines.

     L1D_SPLIT.STORES
	     (Event 49H, Umask 02H) The	number of store	operations that	span
	     two cache lines.

     L1I_MISSES
	     (Event 81H, Umask 00H) The	number of instruction fetch unit
	     misses.

     L1I_READS
	     (Event 80H, Umask 00H) The	number of instruction fetches.

     L2_ADS [,core=core]
	     (Event 21H) The number of cycles that the L2 address bus is in
	     use.

     L2_DBUS_BUSY_RD [,core=core]
	     (Event 23H) The number of cycles during which the L2 data bus is
	     busy transferring data to the core.

     L2_IFETCH [,cachestate=state] [,core=core]
	     (Event 28H) The number of instruction cache line requests from
	     the instruction fetch unit.

     L2_LD [,cachestate=state] [,core=core] [,prefetch=prefetch]
	     (Event 29H) The number of L2 cache	read requests from L1 cache
	     and L2 prefetchers.

     L2_LINES_IN [,core=core] [,prefetch=prefetch]
	     (Event 24H) The number of cache lines allocated in	L2 cache.

     L2_LINES_OUT [,core=core] [,prefetch=prefetch]
	     (Event 26H) The number of L2 cache	lines evicted.

     L2_LOCK [,cachestate=state] [,core=core]
	     (Event 2BH) The number of locked accesses to cache	lines that
	     miss L1 data cache.

     L2_M_LINES_IN [,core=core]
	     (Event 25H) The number of L2 cache	line modifications.

     L2_M_LINES_OUT [,core=core] [,prefetch=prefetch]
	     (Event 27H) The number of modified	lines evicted from L2 cache.

     L2_NO_REQ [,core=core]
	     (Event 32H) The number of cycles during which no L2 cache
	     requests were pending from	a core.

     L2_REJECT_BUSQ [,cachestate=state]	[,core=core] [,prefetch=prefetch]
	     (Event 30H) The number of L2 cache	requests that were rejected.

     L2_RQSTS [,cachestate=state] [,core=core] [,prefetch=prefetch]
	     (Event 2EH) The number of completed L2 cache requests.

     L2_RQSTS.SELF.DEMAND.I_STATE
	     (Event 2EH, Umask 41H) (Alias "LLC	Misses") The number of com-
	     pleted L2 cache demand requests from this core that missed	the L2
	     cache.  This is an	architectural performance event.

     L2_RQSTS.SELF.DEMAND.MESI
	     (Event 2EH, Umask 4FH) (Alias "LLC	References") The number	of
	     completed L2 cache	demand requests	from this core.	 This is an
	     architectural performance event.

     L2_ST [,cachestate=state] [,core=core]
	     (Event 2AH) The number of store operations	that miss the L1 cache
	     and request data from the L2 cache.

     LOAD_BLOCK.L1D
	     (Event 03H, Umask 20H) The	number of loads	blocked	by the L1 data
	     cache.

     LOAD_BLOCK.OVERLAP_STORE
	     (Event 03H, Umask 08H) The	number of loads	that partially overlap
	     an	earlier	store or are aliased with a previous store.

     LOAD_BLOCK.STA
	     (Event 03H, Umask 02H) The	number of loads	blocked	by preceding
	     stores whose address is yet to be calculated.

     LOAD_BLOCK.STD
	     (Event 03H, Umask 04H) The	number of loads	blocked	by preceding
	     stores to the same	address	whose data value is not	known.

     LOAD_BLOCK.UNTIL_RETIRE
	     (Event 03H, Umask 10H) The	number of load operations that were
	     blocked until retirement.

     LOAD_HIT_PRE
	     (Event 4CH, Umask 00H) The	number of load operations that con-
	     flicted with an prefetch to the same cache	line.

     MACHINE_NUKES.SMC
	     (Event C3H, Umask 01H) The	number of times	a program writes to a
	     code section.

     MACHINE_NUKES.MEM_ORDER
	     (Event C3H, Umask 04H) The	number of times	the execution pipeline
	     was restarted due to a memory ordering conflict or	memory disam-
	     biguation misprediction.

     MACRO_INSTS.CISC_DECODED
	     (Event AAH, Umask 08H) The	number of complex instructions
	     decoded.

     MACRO_INSTS.DECODED
	     (Event AAH, Umask 01H) The	number of instructions decoded.

     MEMORY_DISAMBIGUATION.RESET
	     (Event 09H, Umask 01H) The	number of cycles during	which memory
	     disambiguation misprediction occurs.

     MEMORY_DISAMBIGUATION.SUCCESS
	     (Event 09H, Umask 02H) The	number of load operations that were
	     successfully disambiguated.

     MEM_LOAD_RETIRED.DTLB_MISS
	     (Event CBH, Umask 10H) The	number of retired loads	that missed
	     the DTLB.

     MEM_LOAD_RETIRED.L1D_LINE_MISS
	     (Event CBH, Umask 02H) The	number of retired load operations that
	     missed L1 data cache and that sent	a request to L2	cache.	This
	     event is only available on	PMC0.

     MEM_LOAD_RETIRED.L1D_MISS
	     (Event CBH, Umask 01H) The	number of retired load operations that
	     missed L1 data cache.  This event is only available on PMC0.

     MEM_LOAD_RETIRED.L2_LINE_MISS
	     (Event CBH, Umask 08H) The	number of load operations that missed
	     L2	cache and that caused a	bus request.

     MEM_LOAD_RETIRED.L2_MISS
	     (Event CBH, Umask 04H) The	number of load operations that missed
	     L2	cache.

     MUL     (Event 12H, Umask 00H) The	number of multiply operations exe-
	     cuted.  This event	is only	available on PMC1.

     PAGE_WALKS.COUNT
	     (Event 0CH, Umask 01H) The	number of page walks executed due to
	     an	ITLB or	DTLB miss.

     PAGE_WALKS.CYCLES
	     (Event 0CH, Umask 02H) The	number of cycles spent in a page walk
	     caused by an ITLB or DTLB miss.

     PREF_RQSTS_DN
	     (Event F8H, Umask 00H) The	number of downward prefetches issued
	     from the Data Prefetch Logic unit to L2 cache.

     PREF_RQSTS_UP
	     (Event F0H, Umask 00H) The	number of upward prefetches issued
	     from the Data Prefetch Logic unit to L2 cache.

     RAT_STALLS.ANY
	     (Event D2H, Umask 0FH) The	number of stall	cycles due to any of
	     RAT_STALLS.FLAGS RAT_STALLS.FPSW, RAT_STALLS.PARTIAL and
	     RAT_STALLS.ROB_READ_PORT.

     RAT_STALLS.FLAGS
	     (Event D2H, Umask 04H) The	number of cycles execution stalled due
	     to	a flag register	induced	stall.

     RAT_STALLS.FPSW
	     (Event D2H, Umask 08H) The	number of times	the floating point
	     status word was written.

     RAT_STALLS.OTHER_SERIALIZATION_STALLS
	     (Event D2H, Umask 10H, Core2Extreme) The number of	stalls due to
	     other RAT resource	serialization not counted by umask 0FH.

     RAT_STALLS.PARTIAL_CYCLES
	     (Event D2H, Umask 02H) The	number of cycles of added instruction
	     execution latency due to the use of a register that was partially
	     written by	previous instructions.

     RAT_STALLS.ROB_READ_PORT
	     (Event D2H, Umask 01H) The	number of cycles when ROB read port
	     stalls occurred.

     RESOURCE_STALLS.ANY
	     (Event DCH, Umask 1FH) The	number of cycles during	which any
	     resource related stall occurred.

     RESOURCE_STALLS.BR_MISS_CLEAR
	     (Event DCH, Umask 10H) The	number of cycles stalled due to	branch
	     misprediction.

     RESOURCE_STALLS.FPCW
	     (Event DCH, Umask 08H) The	number of cycles stalled due to	writ-
	     ing the floating point control word.

     RESOURCE_STALLS.LD_ST
	     (Event DCH, Umask 04H) The	number of cycles during	which the num-
	     ber of loads and stores in	the pipeline exceeded their limits.

     RESOURCE_STALLS.ROB_FULL
	     (Event DCH, Umask 01H) The	number of cycles when the reorder
	     buffer was	full.

     RESOURCE_STALLS.RS_FULL
	     (Event DCH, Umask 02H) The	number of cycles during	which the RS
	     was full.

     RS_UOPS_DISPATCHED
	     (Event A0H, Umask 00H) The	number of micro-ops dispatched for
	     execution.

     RS_UOPS_DISPATCHED.PORT0
	     (Event A1H, Umask 01H) The	number of cycles micro-ops were	dis-
	     patched for execution on port 0.

     RS_UOPS_DISPATCHED.PORT1
	     (Event A1H, Umask 02H) The	number of cycles micro-ops were	dis-
	     patched for execution on port 1.

     RS_UOPS_DISPATCHED.PORT2
	     (Event A1H, Umask 04H) The	number of cycles micro-ops were	dis-
	     patched for execution on port 2.

     RS_UOPS_DISPATCHED.PORT3
	     (Event A1H, Umask 08H) The	number of cycles micro-ops were	dis-
	     patched for execution on port 3.

     RS_UOPS_DISPATCHED.PORT4
	     (Event A1H, Umask 10H) The	number of cycles micro-ops were	dis-
	     patched for execution on port 4.

     RS_UOPS_DISPATCHED.PORT5
	     (Event A1H, Umask 20H) The	number of cycles micro-ops were	dis-
	     patched for execution on port 5.

     SB_DRAIN_CYCLES
	     (Event 04H, Umask 01H) The	number of cycles while the store
	     buffer is draining.

     SEGMENT_REG_LOADS
	     (Event 06H, Umask 00H) The	number of segment register loads.

     SEG_REG_RENAMES.ANY
	     (Event D5H, Umask 0FH) The	number of times	the any	segment	regis-
	     ter was renamed.

     SEG_REG_RENAMES.DS
	     (Event D5H, Umask 02H) The	number of times	the %ds	register is
	     renamed.

     SEG_REG_RENAMES.ES
	     (Event D5H, Umask 01H) The	number of times	the %es	register is
	     renamed.

     SEG_REG_RENAMES.FS
	     (Event D5H, Umask 04H) The	number of times	the %fs	register is
	     renamed.

     SEG_REG_RENAMES.GS
	     (Event D5H, Umask 08H) The	number of times	the %gs	register is
	     renamed.

     SEG_RENAME_STALLS.ANY
	     (Event D4H, Umask 0FH) The	number of stalls due to	lack of
	     resource to rename	any segment register.

     SEG_RENAME_STALLS.DS
	     (Event D4H, Umask 02H) The	number of stalls due to	lack of	renam-
	     ing resources for the %ds register.

     SEG_RENAME_STALLS.ES
	     (Event D4H, Umask 01H) The	number of stalls due to	lack of	renam-
	     ing resources for the %es register.

     SEG_RENAME_STALLS.FS
	     (Event D4H, Umask 04H) The	number of stalls due to	lack of	renam-
	     ing resources for the %fs register.

     SEG_RENAME_STALLS.GS
	     (Event D4H, Umask 08H) The	number of stalls due to	lack of	renam-
	     ing resources for the %gs register.

     SIMD_ASSIST
	     (Event CDH, Umask 00H) The	number SIMD assists invoked.

     SIMD_COMP_INST_RETIRED.PACKED_DOUBLE
	     (Event CAH, Umask 04H) Then number	of computational SSE2 packed
	     double precision instructions retired.

     SIMD_COMP_INST_RETIRED.PACKED_SINGLE
	     (Event CAH, Umask 01H) Then number	of computational SSE2 packed
	     single precision instructions retired.

     SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE
	     (Event CAH, Umask 08H) Then number	of computational SSE2 scalar
	     double precision instructions retired.

     SIMD_COMP_INST_RETIRED.SCALAR_SINGLE
	     (Event CAH, Umask 02H) Then number	of computational SSE2 scalar
	     single precision instructions retired.

     SIMD_INSTR_RETIRED
	     (Event CEH, Umask 00H) The	number of retired SIMD instructions
	     that use MMX registers.

     SIMD_INST_RETIRED.ANY
	     (Event C7H, Umask 1FH) The	number of streaming SIMD instructions
	     retired.

     SIMD_INST_RETIRED.PACKED_DOUBLE
	     (Event C7H, Umask 04H) The	number of SSE2 packed double precision
	     instructions retired.

     SIMD_INST_RETIRED.PACKED_SINGLE
	     (Event C7H, Umask 01H) The	number of SSE packed single precision
	     instructions retired.

     SIMD_INST_RETIRED.SCALAR_DOUBLE
	     (Event C7H, Umask 08H) The	number of SSE2 scalar double precision
	     instructions retired.

     SIMD_INST_RETIRED.SCALAR_SINGLE
	     (Event C7H, Umask 02H) The	number of SSE scalar single precision
	     instructions retired.

     SIMD_INST_RETIRED.VECTOR
	     (Event C7H, Umask 10H) The	number of SSE2 vector instructions
	     retired.

     SIMD_SAT_INSTR_RETIRED
	     (Event CFH, Umask 00H) The	number of saturated arithmetic SIMD
	     instructions retired.

     SIMD_SAT_UOP_EXEC
	     (Event B1H, Umask 00H) The	number of SIMD saturated arithmetic
	     micro-ops executed.

     SIMD_UOPS_EXEC
	     (Event B0H, Umask 00H) The	number of SIMD micro-ops executed.

     SIMD_UOP_TYPE_EXEC.ARITHMETIC
	     (Event B3H, Umask 20H) The	number of SIMD packed arithmetic
	     micro-ops executed.

     SIMD_UOP_TYPE_EXEC.LOGICAL
	     (Event B3H, Umask 10H) The	number of SIMD packed logical micro-
	     ops executed.

     SIMD_UOP_TYPE_EXEC.MUL
	     (Event B3H, Umask 01H) The	number of SIMD packed multiply micro-
	     ops executed.

     SIMD_UOP_TYPE_EXEC.PACK
	     (Event B3H, Umask 04H) The	number of SIMD pack micro-ops exe-
	     cuted.

     SIMD_UOP_TYPE_EXEC.SHIFT
	     (Event B3H, Umask 02H) The	number of SIMD packed shift micro-ops
	     executed.

     SIMD_UOP_TYPE_EXEC.UNPACK
	     (Event B3H, Umask 08H) The	number of SIMD unpack micro-ops	exe-
	     cuted.

     SNOOP_STALL_DRV [,agent=agent] [,core=core]
	     (Event 7EH) The number of times the bus stalled for snoops.

     SSE_PRE_EXEC.L1
	     (Event 07H, Umask 01H) The	number of PREFETCHT0 instructions exe-
	     cuted.

     SSE_PRE_EXEC.L2
	     (Event 07H, Umask 02H) The	number of PREFETCHT1 instructions exe-
	     cuted.

     SSE_PRE_EXEC.NTA
	     (Event 07H, Umask 00H) The	number of PREFETCHNTA instructions
	     executed.

     SSE_PRE_EXEC.STORES
	     (Event 07H, Umask 03H) The	number of times	SSE non-temporal store
	     instructions were executed.

     SSE_PRE_MISS.L1
	     (Event 4BH, Umask 01H) The	number of times	the PREFETCHT0
	     instruction executed and missed all cache levels.

     SSE_PRE_MISS.L2
	     (Event 4BH, Umask 02H) The	number of times	the PREFETCHT1
	     instruction executed and missed all cache levels.

     SSE_PRE_MISS.NTA
	     (Event 4BH, Umask 00H) The	number of times	the PREFETCHNTA
	     instruction executed and missed all cache levels.

     STORE_BLOCK.ORDER
	     (Event 04H, Umask 02H) The	number of cycles while a store was
	     waiting for another store to be globally observed.

     STORE_BLOCK.SNOOP
	     (Event 04H, Umask 08H) The	number of cycles while a store was
	     blocked due to a conflict with an internal	or external snoop.

     THERMAL_TRIP
	     (Event 3BH, Umask C0H) The	number of thermal trips.

     UOPS_RETIRED.LD_IND_BR
	     (Event C2H, Umask 01H) The	number of micro-ops retired that fused
	     a load with another operation.

     UOPS_RETIRED.STD_STA
	     (Event C2H, Umask 02H) The	number of store	address	calculations
	     that fused	into one micro-op.

     UOPS_RETIRED.MACRO_FUSION
	     (Event C2H, Umask 04H) The	number of times	retired	instruction
	     pairs were	fused into one micro-op.

     UOPS_RETIRED.FUSED
	     (Event C2H, Umask 07H) The	number of fused	micro-ops retired.

     UOPS_RETIRED.NON_FUSED
	     (Event C2H, Umask 8H) The number of non-fused micro-ops retired.

     UOPS_RETIRED.ANY
	     (Event C2H, Umask 0FH) The	number of micro-ops retired.

     X87_OPS_RETIRED.ANY
	     (Event C1H, Umask FEH) The	number of floating point computational
	     instructions retired.

     X87_OPS_RETIRED.FXCH
	     (Event C1H, Umask 01H) The	number of FXCH instructions retired.

   Event Name Aliases
     The following table shows the mapping between the PMC-independent aliases
     supported by Performance Monitoring Counters Interface Library (libpmc,
     -lpmc) and	the underlying hardware	events used.

     Alias		   Event		      PMC Class
     branches		   BR_INST_RETIRED.ANY	      PMC_CLASS_IAP
     branch-mispredicts	   BR_INST_RETIRED.MISPRED    PMC_CLASS_IAP
     ic-misses		   L1I_MISSES		      PMC_CLASS_IAP
     instructions	   INST_RETIRED.ANY_P	      PMC_CLASS_IAF
     interrupts		   HW_INT_RCV		      PMC_CLASS_IAP
     unhalted-cycles	   CPU_CLK_UNHALTED.CORE_P    PMC_CLASS_IAF

SEE ALSO
     pmc(3), pmc.atom(3), pmc.core(3), pmc.iaf(3), pmc.k7(3), pmc.k8(3),
     pmc.p4(3),	pmc.p5(3), pmc.p6(3), pmc.soft(3), pmc.tsc(3), pmc_cpuinfo(3),
     pmclog(3),	hwpmc(4)

HISTORY
     The pmc library first appeared in FreeBSD 6.0.

AUTHORS
     The Performance Monitoring	Counters Interface Library (libpmc, -lpmc)
     library was written by Joseph Koshy <jkoshy@FreeBSD.org>.

FreeBSD	9.3			 June 8, 2009			   FreeBSD 9.3

NAME | LIBRARY | SYNOPSIS | DESCRIPTION | SEE ALSO | HISTORY | AUTHORS

Want to link to this manual page? Use this URL:
<http://www.freebsd.org/cgi/man.cgi?query=pmc.core2&sektion=3&manpath=FreeBSD+9.2-RELEASE>

home | help