CVS log for src/sys/i386/cpufreq/Attic/est.c
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Revision 1.11.2.11: download - view: text, markup, annotated - select for diffs
Fri Mar 4 23:43:10 2011 UTC (11 months, 1 week ago) by jkim
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SVN rev 219279 on 2011-03-04 23:43:10Z by jkim MFC: r219046 Set C1 "I/O then Halt" capability bit for Intel EIST. Some broken BIOSes refuse to load external SSDTs if this bit is unset for _PDC.
Revision 1.11.2.10.4.1: download - view: text, markup, annotated - select for diffs
Tue Dec 21 17:10:29 2010 UTC (13 months, 2 weeks ago) by kensmith
Branches: RELENG_7_4
CVS tags: RELENG_7_4_0_RELEASE
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SVN rev 216618 on 2010-12-21 17:10:29Z by kensmith Copy stable/7 to releng/7.4 in preparation for FreeBSD-7.4 release. Approved by: re (implicit)
Revision 1.24.2.3
Tue Nov 9 01:57:56 2010 UTC (15 months ago) by attilio
Branches: RELENG_8
CVS tags: RELENG_8_2_BP, RELENG_8_2_0_RELEASE, RELENG_8_2
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SVN rev 215026 on 2010-11-09 01:57:56Z by attilio MFC r204309, r204313 and r204319 by nyan: Introduce the x86 subtree for code shared between amd64, i386 and pc98. Differently from the HEAD version, the headers are not moved around, in order to avoid breaking the KPI but it can be eventually done once the core mechanism of r214629 is MFCed. MFCing this patch does allow for simpler MFCs handling on i386/amd64 specific code. Sponsored by: Sandvine Incorporated
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Mon Jun 14 02:09:06 2010 UTC (19 months, 3 weeks ago) by kensmith
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CVS tags: RELENG_8_1_0_RELEASE
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SVN rev 209145 on 2010-06-14 02:09:06Z by kensmith Copy stable/8 to releng/8.1 in preparation for 8.1-RC1. Approved by: re (implicit)
Revision 1.28
Thu Feb 25 14:13:39 2010 UTC (23 months, 2 weeks ago) by attilio
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SVN rev 204309 on 2010-02-25 14:13:39Z by attilio Introduce the new kernel sub-tree x86 which should contain all the code shared and generalized between our current amd64, i386 and pc98. This is just an initial step that should lead to a more complete effort. For the moment, a very simple porting of cpufreq modules, BIOS calls and the whole MD specific ISA bus part is added to the sub-tree but ideally a lot of code might be added and more shared support should grow. Sponsored by: Sandvine Incorporated Reviewed by: emaste, kib, jhb, imp Discussed on: arch MFC: 3 weeks
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Wed Feb 10 00:26:20 2010 UTC (23 months, 4 weeks ago) by kensmith
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CVS tags: RELENG_7_3_0_RELEASE
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SVN rev 203736 on 2010-02-10 00:26:20Z by kensmith Copy stable/7 to releng/7.3 as part of the 7.3-RELEASE process. Approved by: re (implicit)
Revision 1.24.2.2: download - view: text, markup, annotated - select for diffs
Thu Nov 26 15:11:19 2009 UTC (2 years, 2 months ago) by mav
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SVN rev 199834 on 2009-11-26 15:11:19Z by mav MFC r199268, r199269, r199273: Core2Duo/Core2Quad CPUs are unable to control frequency of single CPU core, only pair of them. As result, both cores are running on highest one of requested frequencies, and that is reported by status register. Such behavior confuses frequency validation logic, as it runs on only one core, as SMP is not yet launched, making EIST completely unusable. Disable frequency validation by default, for systems with more then one CPU, until we can implement it properly. It looks like making more harm now then benefits. Add 'hw.est.strict' loader tunable to control it. PR: amd64/140506
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Sat Nov 14 16:20:07 2009 UTC (2 years, 2 months ago) by mav
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SVN rev 199273 on 2009-11-14 16:20:07Z by mav Previous solution appeared to be unsufficient. After additional testing I have found that it is not only desktop CPUs problem. but mobile also. Probably AP on laptops just started initially at lower frequency, hiding the problem. Disable frequency validation by default, for systems with more then one CPU, until we can implement it properly. It looks like making more harm now then benefits. Add 'hw.est.strict' loader tunable to control it. Now my iXsystems Invincibook is able to run at 800MHz lowest frequency, instead of 1200MHz before, when 800MHz was incorrectly reported invalid.
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Sat Nov 14 14:29:18 2009 UTC (2 years, 2 months ago) by mav
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SVN rev 199269 on 2009-11-14 14:29:18Z by mav Retry only once, if BIOS is completely broken and gives zero freqs.
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Sat Nov 14 14:16:02 2009 UTC (2 years, 2 months ago) by mav
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SVN rev 199268 on 2009-11-14 14:16:02Z by mav Desktop Core2Duo/Core2Quad CPUs are unable to control frequency of single CPU core, only pair of them. As result, both cores are running on highest one of requested frequencies, and that is reported by status register. Such behavior confuses frequency validation logic, as it runs on only one core, as SMP is not yet launched, making EIST completely unusable. To workaround this, add check for validation result. If we haven't found at least two usable frequencies, then probably we are looking bad and have to trust data provided by BIOS as-is.
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Sun Oct 25 01:10:29 2009 UTC (2 years, 3 months ago) by kensmith
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SVN rev 198460 on 2009-10-25 01:10:29Z by kensmith Copy stable/8 to releng/8.0 as part of 8.0-RELEASE release procedure. Approved by: re (implicit)
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Mon Aug 3 08:13:06 2009 UTC (2 years, 6 months ago) by kensmith
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SVN rev 196045 on 2009-08-03 08:13:06Z by kensmith Copy head to stable/8 as part of 8.0 Release cycle. Approved by: re (Implicit)
Revision 1.11.2.10: download - view: text, markup, annotated - select for diffs
Mon Jul 13 22:13:13 2009 UTC (2 years, 6 months ago) by jkim
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SVN rev 195667 on 2009-07-13 22:13:13Z by jkim MFC: Replace remaining cpu_vendor with cpu_vendor_id and add basic VIA Nano processor support for amd64 and i386. r186797 - Add Centaur/IDT/VIA vendor ID for Nano family. r187101 - Allow VIA Nano processors to boot FreeBSD/amd64. r187117 - Replace more cpu_vendor with cpu_vendor_id. r187118 - Add basic i386 support for VIA Nano processors. r187157 - Enable MSI support for VIA Nano processors on i386. r187594 - Replace more cpu_vendor with cpu_vendor_id. r187597 - Include a missing header file. r187598 - VIA Nano processor has P-state invariant TSC. r187633 - Add more VIA bridges to agp_via.c.
Revision 1.11.2.9: download - view: text, markup, annotated - select for diffs
Tue Jun 30 17:10:08 2009 UTC (2 years, 7 months ago) by avg
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SVN rev 195197 on 2009-06-30 17:10:08Z by avg MFC 185295, 185341, 185343: cpu identification improvements Goal of this MFC is to minimize unnecessary code differences between head and the branch, and to improve/fix invariant TSC detection for a wide range of CPUs. 185295 by takawata: Honor AMDPM_TSC_INVARIANT for Intel CPUs (i386 only) 185341 by jkim: Introduce cpu_vendor_id... 185343 by jkim: Use newly introduced cpu_vendor_id... These revision are bundled together because all intermediate revisions have one or more of the following deficiencies: o AMDPM_TSC_INVARIANT bit (CPUID.0x80000007.EDX[8]) is not honored for Intel CPUs; o AMD-specific CPU model/revision checks are performed on Intel CPUs. Nod from: jkim
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Fri Jun 5 18:44:36 2009 UTC (2 years, 8 months ago) by jkim
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SVN rev 193530 on 2009-06-05 18:44:36Z by jkim Import ACPICA 20090521.
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Wed Apr 15 03:14:26 2009 UTC (2 years, 9 months ago) by kensmith
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SVN rev 191087 on 2009-04-15 03:14:26Z by kensmith Create releng/7.2 from stable/7 in preparation for 7.2-RELEASE. Approved by: re (implicit)
Revision 1.11.2.8: download - view: text, markup, annotated - select for diffs
Wed Jan 21 15:01:36 2009 UTC (3 years ago) by jhb
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SVN rev 187529 on 2009-01-21 15:01:36Z by jhb MFC: If we are unable to obtain a frequency list from either ACPI or the static tables, then attempt to build a simple list containing just the high and low frequencies if the hw.est.msr_info tunable is set to 1. By default this is disabled.
Revision 1.23: download - view: text, markup, annotated - select for diffs
Mon Jan 5 21:51:49 2009 UTC (3 years, 1 month ago) by jkim
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SVN rev 186797 on 2009-01-05 21:51:49Z by jkim Add Centaur/IDT/VIA vendor ID for Nano family, which has long mode support.
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Wed Nov 26 19:25:13 2008 UTC (3 years, 2 months ago) by jkim
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SVN rev 185341 on 2008-11-26 19:25:13Z by jkim Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "..."). Reviewed by: jhb, peter (early amd64 version)
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Tue Nov 25 02:59:29 2008 UTC (3 years, 2 months ago) by kensmith
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SVN rev 185281 on 2008-11-25 02:59:29Z by kensmith Create releng/7.1 in preparation for moving into RC phase of 7.1 release cycle. Approved by: re (implicit)
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Thu Oct 2 02:57:24 2008 UTC (3 years, 4 months ago) by kensmith
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SVN rev 183531 on 2008-10-02 02:57:24Z by kensmith Create releng/6.4 from stable/6 in preparation for 6.4-RC1. Approved by: re (implicit)
Revision 1.11.2.7: download - view: text, markup, annotated - select for diffs
Wed Sep 17 20:12:24 2008 UTC (3 years, 4 months ago) by jhb
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SVN rev 183119 on 2008-09-17 20:12:24Z by jhb MFC: Add a proper detach method to est(4). Approved by: re (kib)
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Wed Sep 10 17:41:41 2008 UTC (3 years, 4 months ago) by jhb
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SVN rev 182908 on 2008-09-10 17:41:41Z by jhb Add a proper detach method to the est(4) driver using cpufreq_unregister(). MFC after: 1 week
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Tue Aug 26 17:43:46 2008 UTC (3 years, 5 months ago) by jhb
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SVN rev 182201 on 2008-08-26 17:43:46Z by jhb Disable the code to generate a simple table from the status MSR by default. This can be enabled by setting the 'hw.est.msr_info' tunable to 1.
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Sat Aug 23 12:53:42 2008 UTC (3 years, 5 months ago) by jhb
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SVN rev 182048 on 2008-08-23 12:53:42Z by jhb If we are unable to obtain a frequency list from either ACPI or the static tables, then attempt to build a simple list containing just the high and low frequencies based on the current CPU frequency calculated during boot and the contents of the MSR. MFC after: 1 month
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Wed Aug 20 18:33:09 2008 UTC (3 years, 5 months ago) by jhb
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SVN rev 181935 on 2008-08-20 18:33:09Z by jhb MFC: Attach the cpufreq child devices with specific orders to enforce relative priority of some of the drivers that manage the same state (e.g. ichss0 vs est0).
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Wed Aug 13 16:09:40 2008 UTC (3 years, 5 months ago) by jhb
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SVN rev 181691 on 2008-08-13 16:09:40Z by jhb Attach the cpufreq child devices with specific orders to enforce relative priority of some of the drivers that manage the same state (e.g. ichss0 vs est0). Specifically, powernow, est, and p4tcc are added at order 10, ichss at order 20, and smist at order 30. Previously, some laptops were seeing both ichss0 and est0 attaching and stomping on each other. XXX: This isn't quite ideal, but works with the existing hacks, I think what we really want instead is a single "speedstep0" device for CPUs that the ichss, est, and smist drivers probe (but with differing priorities). MFC after: 1 week
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Fri Jun 27 00:56:36 2008 UTC (3 years, 7 months ago) by jhb
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SVN rev 180045 on 2008-06-27 00:56:36Z by jhb MFC: After probing the available frequency settings, restore the CPU to run at whatever frequency it started at.
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Fri Jun 27 00:48:23 2008 UTC (3 years, 7 months ago) by jhb
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SVN rev 180044 on 2008-06-27 00:48:23Z by jhb MFC: After probing the available frequency settings, restore the CPU to run at whatever frequency it started at.
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Fri May 30 22:01:09 2008 UTC (3 years, 8 months ago) by jhb
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After probing the available frequency settings, restore the CPU to run at whatever frequency it started at instead of always picking the highest frequency. The first version of this driver attempted to do this, but it set the speed to the first frequency in the list rather than the value it had saved. MFC after: 1 week Discussed with: rpaulo, phk
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Fri May 2 10:16:41 2008 UTC (3 years, 9 months ago) by rpaulo
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Remove unused variable saved_id16. Pointy hat to: me Pointed out by: jhb MFC after: 1 week
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Thu May 1 20:15:01 2008 UTC (3 years, 9 months ago) by jhb
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MFC: A few fixes. - Increase time we wait for things to settle to 1 millisecond, 10 microseconds is too short. - In est_acpi_info(), initialize count.
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Tue Apr 8 09:38:15 2008 UTC (3 years, 10 months ago) by phk
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MFC: 1.13: Use correct bitmask for checking CPU identities. 1.16: Add XXX comment about the table in general.
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Mon Mar 17 18:31:06 2008 UTC (3 years, 10 months ago) by jhb
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MFC: Use cpu_feature2 and don't free anything in detach.
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Mon Mar 17 18:30:37 2008 UTC (3 years, 10 months ago) by jhb
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MFC: Use cpu_feature2 and don't free anything in detach.
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Mon Mar 17 09:01:43 2008 UTC (3 years, 10 months ago) by phk
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Increase time we wait for things to settle to 1 millisecond, 10 microseconds is too short. Always set the cpu to the highest frequency so that we get through boot and don't handicap cpus where powerd(8) is not used.
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Fri Mar 14 02:57:46 2008 UTC (3 years, 10 months ago) by gibbs
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MFC: In est_acpi_info(), initialize count before passing its pointer to CPUFREQ_DRV_SETTINGS().
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Mon Mar 10 22:00:35 2008 UTC (3 years, 11 months ago) by jhb
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- Don't execute cpuid to fetch the features. We already have the features present in cpu_feature2. Also, use CPUID2_EST rather than a magic number. - Don't free the ACPI settings list in detach if we are going to fail the request. Otherwise an attempt to kldunload est would free the array but the driver would keep trying to use it. MFC after: 1 week
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Sat Mar 8 14:14:35 2008 UTC (3 years, 11 months ago) by rpaulo
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MFC r1.12: Validate the id16 values gathered from ACPI (previously a TODO item). Style changes by me and njl. Submitted by: Takeharu KATO <takeharu1219 at ybb.ne.jp> PR: 119350
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Sat Mar 8 14:12:35 2008 UTC (3 years, 11 months ago) by rpaulo
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MFC r1.12: Validate the id16 values gathered from ACPI (previously a TODO item). Style changes by me and njl. Submitted by: Takeharu KATO <takeharu1219 at ybb.ne.jp> PR: 119350
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Sat Mar 1 21:58:34 2008 UTC (3 years, 11 months ago) by gibbs
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In est_acpi_info(), initialize count before passing its pointer to CPUFREQ_DRV_SETTINGS(). The value of count on input is used to prefent overflow of the settings buffer passed into CPUFREQ_DRV_SETTINGS(). This corrects the "est: CPU supports Enhanced Speedstep, but is not recognized." error on my system. MFC after: 1 week
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Thu Feb 28 19:10:42 2008 UTC (3 years, 11 months ago) by rpaulo
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Validate the id16 values gathered from ACPI (previously a TODO item). Style changes by me and njl. Approved by: njl (mentor) Reviewed by: njl (mentor) Submitted by: Takeharu KATO <takeharu1219 at ybb.ne.jp> PR: 119350 MFC after: 1 week
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Mon May 29 22:40:03 2006 UTC (5 years, 8 months ago) by njl
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CVS tags: RELENG_6_3_BP, RELENG_6_3_0_RELEASE, RELENG_6_3, RELENG_6_2_BP, RELENG_6_2_0_RELEASE, RELENG_6_2
Diff to: previous 1.7: preferred, colored
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MFC: newer Intel and VIA C7-M support
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Thu May 11 17:35:44 2006 UTC (5 years, 9 months ago) by njl
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Add support for the VIA C7-M processor family. Remove an unnecessary check of the table's bus clock. CPUs that support this feature export only the high/low settings via the MSR, packed into 32 bits. Hardware from: Centaur Technologies MFC after: 1 week
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Sat Feb 25 04:55:38 2006 UTC (5 years, 11 months ago) by cperciva
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Add frequency-voltage tables for Intel 778, 758, 773, 753, and 733J processors. Obtained from: Intel Datasheet 302189-008
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Sun Jul 31 06:42:27 2005 UTC (6 years, 6 months ago) by cperciva
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Print cpu_vendor and the MSR value if we don't support this processor even though we're not asking people to contact us. Requested by: njl
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Sun Jul 31 01:57:05 2005 UTC (6 years, 6 months ago) by cperciva
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Remove the instruction to "contact the maintainer" for unrecognized CPUs. Intel refuses to give me the information I need, and getting more emails about this doesn't help.
Revision 1.7.4.1: download - view: text, markup, annotated - select for diffs
Thu Jul 21 09:20:10 2005 UTC (6 years, 6 months ago) by bruno
Branches: RELENG_5
CVS tags: RELENG_5_5_BP, RELENG_5_5_0_RELEASE, RELENG_5_5
Diff to: previous 1.7: preferred, colored; next MAIN 1.8: preferred, colored
Changes since revision 1.7: +0 -0 lines
MFC: add all other cpufreq specific drivers that do not belong to acpi. Approved by: njl, imp (mentor)
Revision 1.7: download - view: text, markup, annotated - select for diffs
Sun Apr 10 19:57:47 2005 UTC (6 years, 10 months ago) by njl
Branches: MAIN
CVS tags: RELENG_6_BP, RELENG_6_1_BP, RELENG_6_1_0_RELEASE, RELENG_6_1, RELENG_6_0_BP, RELENG_6_0_0_RELEASE, RELENG_6_0
Branch point for: RELENG_6, RELENG_5
Diff to: previous 1.6: preferred, colored
Changes since revision 1.6: +6 -6 lines
Properly terminate the table generated from ACPI info. The cpufreq settings are length-counted while the EST table is null-terminated. This fixes extra garbage states being reported with ACPI probing.
Revision 1.6: download - view: text, markup, annotated - select for diffs
Mon Apr 4 15:51:12 2005 UTC (6 years, 10 months ago) by njl
Branches: MAIN
Diff to: previous 1.5: preferred, colored
Changes since revision 1.5: +21 -1 lines
Add support for _PDC/_OSC by advertising that we support direct access to the PERF_CTL/STS MSRs via the new acpi_get_features() method. This should allow newer systems to use SpeedStep.
Revision 1.5: download - view: text, markup, annotated - select for diffs
Mon Mar 21 06:43:25 2005 UTC (6 years, 10 months ago) by njl
Branches: MAIN
Diff to: previous 1.4: preferred, colored
Changes since revision 1.4: +166 -77 lines
Add support for probing EST settings from ACPI. This should handle more modern CPUs that have multiple VID#s that aren't detectable via public methods. We use the control value from acpi_perf as the id16 for setting a given frequency.
Revision 1.4: download - view: text, markup, annotated - select for diffs
Sun Feb 27 02:43:02 2005 UTC (6 years, 11 months ago) by njl
Branches: MAIN
Diff to: previous 1.3: preferred, colored
Changes since revision 1.3: +4 -0 lines
Make a pass through all drivers checking specs for desired behavior on SMP systems. It appears all drivers except ichss should attach to each CPU and that settings should be performed on each CPU. Add comments about this. Also, add a guard for p4tcc's identify method being called more than once.
Revision 1.3: download - view: text, markup, annotated - select for diffs
Thu Feb 24 20:20:11 2005 UTC (6 years, 11 months ago) by njl
Branches: MAIN
Diff to: previous 1.2: preferred, colored
Changes since revision 1.2: +3 -4 lines
Correct an off-by-one error in the number of settings est announces. The extraneous "0" state was not fatal but useless.
Revision 1.2: download - view: text, markup, annotated - select for diffs
Tue Feb 22 06:31:45 2005 UTC (6 years, 11 months ago) by njl
Branches: MAIN
Diff to: previous 1.1: preferred, colored
Changes since revision 1.1: +3 -0 lines
Support disabling individual cpufreq drivers with hints, e.g., hint.ichss.0.disabled="1"
Revision 1.1: download - view: text, markup, annotated - select for diffs
Sun Feb 20 20:27:59 2005 UTC (6 years, 11 months ago) by njl
Branches: MAIN
Add the Enhanced SpeedStep driver (EST). Currently, this driver only works on the previous generation of Pentium-M processors (Banias). Support for Dothan and later processors involves working with acpi_perf(4) to extract information about supported states. This driver should work on MP systems including HTT. It is experimental and may have a few bugs but has been tested to not crash at least. Thanks to Colin Percival for his initial work on this driver.