CVS log for ports/cad/iverilog/pkg-plist
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Default branch: MAIN
Revision 1.10: download - view: text, markup, annotated - select for diffs
Tue Jun 9 12:58:04 2009 UTC (2 years, 8 months ago) by stas
Branches: MAIN
CVS tags: RELEASE_9_0_0, RELEASE_8_2_0, RELEASE_8_1_0, RELEASE_8_0_0, RELEASE_7_4_0, RELEASE_7_3_0, RELEASE_6_EOL, HEAD
Diff to: previous 1.9: preferred, colored
Changes since revision 1.9: +13 -8 lines
- Update to 0.9.1.
Revision 1.9: download - view: text, markup, annotated - select for diffs
Fri Jan 23 22:04:50 2009 UTC (3 years ago) by stas
Branches: MAIN
CVS tags: RELEASE_7_2_0
Diff to: previous 1.8: preferred, colored
Changes since revision 1.8: +6 -5 lines
- Update to 0.8.7.
Revision 1.8: download - view: text, markup, annotated - select for diffs
Tue Oct 3 13:34:22 2006 UTC (5 years, 4 months ago) by stas
Branches: MAIN
CVS tags: RELEASE_7_1_0, RELEASE_7_0_0, RELEASE_6_4_0, RELEASE_6_3_0, RELEASE_6_2_0, RELEASE_5_EOL, RELEASE_4_EOL, PRE_XORG_7
Diff to: previous 1.7: preferred, colored
Changes since revision 1.7: +4 -1 lines
- Update to 0.8.2 - Fix compiling with gcc 4.1 - Change my email Approved by: sem (mentor)
Revision 1.7: download - view: text, markup, annotated - select for diffs
Fri Nov 5 13:16:52 2004 UTC (7 years, 3 months ago) by arved
Branches: MAIN
CVS tags: RELEASE_6_1_0, RELEASE_6_0_0, RELEASE_5_5_0, RELEASE_5_4_0, RELEASE_4_11_0
Diff to: previous 1.6: preferred, colored
Changes since revision 1.6: +1 -0 lines
Update to 0.8 PR: 72949 Submitted by: Joachim Strombergson <watchman@ludd.ltu.se>
Revision 1.6: download - view: text, markup, annotated - select for diffs
Wed Dec 17 16:02:50 2003 UTC (8 years, 1 month ago) by linimon
Branches: MAIN
CVS tags: RELEASE_5_3_0, RELEASE_4_10_0
Diff to: previous 1.5: preferred, colored
Changes since revision 1.5: +9 -1 lines
Update to 20031202 snapshot. Summary of changes listed on ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20031202.txt: Combination 64bit/32bit runtime support now works fully on AMD64 systems; wait on lists of named events now works; there is no longer a common iverilog.conf, instead there are target specific foo.conf files with a new and cleaner format; 64bit values are more portably handled; several synthesis bugs related to the control inputs of flip-flops have been fixed. Committer is marking this BROKEN on 4.x while we investigate install problems. It works on 5.x only for now. PR: ports/60162 Submitted by: Joachim Strombergson <watchman@ludd.luth.se> (maintainer)
Revision 1.5: download - view: text, markup, annotated - select for diffs
Mon Oct 27 10:02:34 2003 UTC (8 years, 3 months ago) by linimon
Branches: MAIN
CVS tags: RELEASE_5_2_1, RELEASE_5_2_0
Diff to: previous 1.4: preferred, colored
Changes since revision 1.4: +1 -0 lines
Maintainer Update to latest snapshot. Changes: add AMD64 support (experimental); time 0 race resolution; identation cleanup; manpage update. PR: ports/58320
Revision 1.4: download - view: text, markup, annotated - select for diffs
Fri May 16 18:18:38 2003 UTC (8 years, 8 months ago) by will
Branches: MAIN
CVS tags: RELEASE_5_1_0, RELEASE_4_9_0
Diff to: previous 1.3: preferred, colored
Changes since revision 1.3: +4 -16 lines
Fix this port and remove BROKEN.
Revision 1.3: download - view: text, markup, annotated - select for diffs
Fri Jan 31 17:49:45 2003 UTC (9 years ago) by keichii
Branches: MAIN
CVS tags: RELEASE_4_8_0
Diff to: previous 1.2: preferred, colored
Changes since revision 1.2: +6 -0 lines
Update to iverilog 0.7 Submitted by: Joachim Str?mbergson <watchman@ludd.luth.se>
Revision 1.2: download - view: text, markup, annotated - select for diffs
Thu Sep 19 03:04:23 2002 UTC (9 years, 4 months ago) by kris
Branches: MAIN
CVS tags: RELEASE_5_0_0, RELEASE_4_7_0
Diff to: previous 1.1: preferred, colored
Changes since revision 1.1: +4 -0 lines
Add missing files
Revision 1.1: download - view: text, markup, annotated - select for diffs
Tue Feb 13 11:02:15 2001 UTC (10 years, 11 months ago) by ijliao
Branches: MAIN
CVS tags: RELEASE_5_0_DP1, RELEASE_4_6_2, RELEASE_4_6_1, RELEASE_4_6_0, RELEASE_4_5_0, RELEASE_4_4_0, RELEASE_4_3_0
add iverilog, a Verilog simulation and synthesis tool