CVS log for ports/cad/iverilog/pkg-descr
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Default branch: MAIN
Revision 1.3: download - view: text, markup, annotated - select for diffs
Fri Nov 4 18:16:30 2011 UTC (3 months ago) by pawel
Branches: MAIN
CVS tags: RELEASE_9_0_0, HEAD
Diff to: previous 1.2: preferred, colored
Changes since revision 1.2: +1 -1 lines
- Update to version 0.9.5 - Add LICENSE - Update project homepage PR: ports/162280 Submitted by: Niclas Zeising <niclas.zeising@gmail.com> (maintainer)
Revision 1.2: download - view: text, markup, annotated - select for diffs
Fri Jul 30 14:51:36 2010 UTC (18 months, 1 week ago) by olgeni
Branches: MAIN
CVS tags: RELEASE_8_2_0, RELEASE_7_4_0, RELEASE_6_EOL
Diff to: previous 1.1: preferred, colored
Changes since revision 1.1: +1 -1 lines
Fix a few typos in ports/cad.
Revision 1.1: download - view: text, markup, annotated - select for diffs
Tue Feb 13 11:02:15 2001 UTC (10 years, 11 months ago) by ijliao
Branches: MAIN
CVS tags: RELEASE_8_1_0, RELEASE_8_0_0, RELEASE_7_3_0, RELEASE_7_2_0, RELEASE_7_1_0, RELEASE_7_0_0, RELEASE_6_4_0, RELEASE_6_3_0, RELEASE_6_2_0, RELEASE_6_1_0, RELEASE_6_0_0, RELEASE_5_EOL, RELEASE_5_5_0, RELEASE_5_4_0, RELEASE_5_3_0, RELEASE_5_2_1, RELEASE_5_2_0, RELEASE_5_1_0, RELEASE_5_0_DP1, RELEASE_5_0_0, RELEASE_4_EOL, RELEASE_4_9_0, RELEASE_4_8_0, RELEASE_4_7_0, RELEASE_4_6_2, RELEASE_4_6_1, RELEASE_4_6_0, RELEASE_4_5_0, RELEASE_4_4_0, RELEASE_4_3_0, RELEASE_4_11_0, RELEASE_4_10_0, PRE_XORG_7
add iverilog, a Verilog simulation and synthesis tool
