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CVS log for ports/cad/gplcver/pkg-descr

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Revision 1.2: download - view: text, markup, annotated - select for diffs
Thu Jun 16 10:41:31 2011 UTC (7 months, 3 weeks ago) by bapt
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CVS tags: RELEASE_9_0_0, HEAD
Diff to: previous 1.1: preferred, colored
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Thu Dec 29 03:48:58 2005 UTC (6 years, 1 month ago) by edwin
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CVS tags: RELEASE_8_2_0, RELEASE_8_1_0, RELEASE_8_0_0, RELEASE_7_4_0, RELEASE_7_3_0, RELEASE_7_2_0, RELEASE_7_1_0, RELEASE_7_0_0, RELEASE_6_EOL, RELEASE_6_4_0, RELEASE_6_3_0, RELEASE_6_2_0, RELEASE_6_1_0, RELEASE_5_EOL, RELEASE_5_5_0, RELEASE_4_EOL, PRE_XORG_7
[NEW PORT] cad/gplcver: A Verilog HDL simulator

	GPL Cver is a full 1995 P1364 Verilog standard HDL simulator.
	It also implements some of the 2001 P1364 standard features
	including all three PLI interfaces (tf_, acc_ and vpi_) as
	defined in the 2001 Language Reference Manual (LRM).

	Verilog is the name for both a language for describing
	electronic hardware called a hardware description language
	(HDL) and the name of the program that simulates HDL circuit
	descriptions to verify that described circuits will function
	correctly when the are constructed. Verilog is used only
	for describing digital logic circuits. Other HDLs such as
	Spice are used for describing analog circuits. There is an
	IEEE standard named P1364 that standardizes the Verilog HDL
	and the behavior of Verilog simulators.  Verilog is officially
	defined in the IEEE P1364 Language Reference Manual (LRM)
	that can be purchased from IEEE. There are many good books
	for learning that teach the Verilog HDL and/or that teach
	digital circuit design using Verilog.

	WWW: http://www.pragmatic-c.com/gpl-cver/

PR:		ports/80968
Submitted by:	Ying-Chieh Liao <ijliao@csie.nctu.edu.tw>
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