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Revision 1.10: download - view: text, markup, annotated - select for diffs
Thu Jun 16 10:41:31 2011 UTC (7 months, 3 weeks ago) by bapt
Branches: MAIN
CVS tags: RELEASE_9_0_0, HEAD
Diff to: previous 1.9: preferred, colored
Changes since revision 1.9: +1 -1 lines
Point to the new home
Make it fetchable again
Revision 1.9: download - view: text, markup, annotated - select for diffs
Mon Oct 27 15:59:26 2008 UTC (3 years, 3 months ago) by tabthorpe
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CVS tags: RELEASE_8_2_0, RELEASE_8_1_0, RELEASE_8_0_0, RELEASE_7_4_0, RELEASE_7_3_0, RELEASE_7_2_0, RELEASE_6_EOL
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Changes since revision 1.8: +1 -1 lines
- Reassign to ports
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Thu Aug 23 03:59:55 2007 UTC (4 years, 5 months ago) by tabthorpe
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CVS tags: RELEASE_7_1_0, RELEASE_7_0_0, RELEASE_6_4_0, RELEASE_6_3_0, RELEASE_5_EOL
Diff to: previous 1.7: preferred, colored
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- change maintainer address on ports I maintain

Approved by:	clsung (mentor)
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Sat Jul 21 01:21:52 2007 UTC (4 years, 6 months ago) by ijliao
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'actually' pass maintainership
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Sat Jul 21 01:20:50 2007 UTC (4 years, 6 months ago) by ijliao
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upgrade to 2.12.a
pass maintainership to submitter

PR:		114768
Submitted by:	Thomas Abthorpe <thomas@goodking.ca>
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Thu Aug 3 03:26:38 2006 UTC (5 years, 6 months ago) by clsung
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CVS tags: RELEASE_6_2_0, RELEASE_4_EOL, PRE_XORG_7
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- maintainer is a committer
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Fri Jan 20 14:18:34 2006 UTC (6 years ago) by arved
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CVS tags: RELEASE_6_1_0, RELEASE_5_5_0
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Fix build on sparc
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Thu Jan 19 23:31:12 2006 UTC (6 years ago) by kris
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BROKEN on sparc64: Does not compile
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Wed Jan 4 05:56:54 2006 UTC (6 years, 1 month ago) by edwin
Branches: MAIN
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Fix maintainership (set to submitter)
Revision 1.1: download - view: text, markup, annotated - select for diffs
Thu Dec 29 03:48:58 2005 UTC (6 years, 1 month ago) by edwin
Branches: MAIN
[NEW PORT] cad/gplcver: A Verilog HDL simulator

	GPL Cver is a full 1995 P1364 Verilog standard HDL simulator.
	It also implements some of the 2001 P1364 standard features
	including all three PLI interfaces (tf_, acc_ and vpi_) as
	defined in the 2001 Language Reference Manual (LRM).

	Verilog is the name for both a language for describing
	electronic hardware called a hardware description language
	(HDL) and the name of the program that simulates HDL circuit
	descriptions to verify that described circuits will function
	correctly when the are constructed. Verilog is used only
	for describing digital logic circuits. Other HDLs such as
	Spice are used for describing analog circuits. There is an
	IEEE standard named P1364 that standardizes the Verilog HDL
	and the behavior of Verilog simulators.  Verilog is officially
	defined in the IEEE P1364 Language Reference Manual (LRM)
	that can be purchased from IEEE. There are many good books
	for learning that teach the Verilog HDL and/or that teach
	digital circuit design using Verilog.

	WWW: http://www.pragmatic-c.com/gpl-cver/

PR:		ports/80968
Submitted by:	Ying-Chieh Liao <ijliao@csie.nctu.edu.tw>
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