CVS log for ports/cad/cider/files/Attic/patch-ag
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Revision 1.3
Fri Nov 21 22:32:47 2003 UTC (8 years, 2 months ago) by pav
Branches: MAIN
CVS tags: HEAD
FILE REMOVED
Changes since revision 1.2: +0 -0 lines
- Don't link with randline PR: ports/58238 Submitted by: AMAKAWA Shuhei <sa264@cam.ac.uk> (maintainer) Approved by: adamw (mentor)
Revision 1.2: download - view: text, markup, annotated - select for diffs
Wed Dec 29 21:32:09 1999 UTC (12 years, 1 month ago) by steve
Branches: MAIN
CVS tags: RELEASE_5_1_0, RELEASE_5_0_DP1, RELEASE_5_0_0, RELEASE_4_9_0, RELEASE_4_8_0, RELEASE_4_7_0, RELEASE_4_6_2, RELEASE_4_6_1, RELEASE_4_6_0, RELEASE_4_5_0, RELEASE_4_4_0, RELEASE_4_3_0, RELEASE_4_2_0, RELEASE_4_1_1, RELEASE_4_1_0, RELEASE_4_0_0, RELEASE_3_5_0
Diff to: previous 1.1: preferred, colored
Changes since revision 1.1: +2 -2 lines
* Do not set NO_WRKSUBDIR to yes. Specify WRKSRC. * Respect CFLAGS. * Make less use of __FreeBSD__. * Use more system-defined make variables. PR: 15746 Submitted by: maintainer
Revision 1.1: download - view: text, markup, annotated - select for diffs
Sat Dec 25 15:40:46 1999 UTC (12 years, 1 month ago) by steve
Branches: MAIN
cider version 1b1 A mixed-level circuit and device simulator (includes SPICE3). PR: 15462 Submitted by: AMAKAWA Shuhei <amakawa@jp.FreeBSD.org>